M54HC4040| Datasheet

M54HC4040, M54HC4040D, M54HC4040K, M54HC4040K1

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M54HC4040
RAD-HARD 12 STAGE BINARY COUNTER
s

s s

HIGH SPEED: fMAX = 70 MHz (TYP.) at VCC = 6V LOW POWER DISSIPATION: ICC =4uA(MAX.) at TA=25 C HIGH NOISE IMMUNITY: VNIH = VNIL = 28% VCC (MIN.) SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 4mA (MIN) BALANCED PROPAGATION DELAYS: tPLH tPHL WIDE OPERATING VOLTAGE RANGE: VCC (OPR) = 2V to 6V PIN AND FUNCTION COMPATIBLE WITH 54 SERIES 4040 SPACE GRADE-1: ESA SCC QUALIFIED 50 krad QUALIFIED, 100 krad AVAILABLE ON REQUEST NO SEL UNDER HIGH LET HEAVY IONS IRRADIATION DEVICE FULLY COMPLIANT WITH SCC-9204-069

DILC-16

FPC-16

ORDER CODES
PACKAGE DILC FPC FM M54HC4040D M54HC4040K EM M54HC4040D1 M54HC4040K1

DESCRIPTION The M54HC4040 is an high speed CMOS 12 STAGE BINARY COUNTER fabricated with silicon gate C2MOS technology.

A clear input is used to reset the counter to the all low level state. A high level on CLEAR accomplishes the reset function. A negative transition on the CLOCK input increments the counter by one. For M54HC4040 each division stage has an output; the final frequency is 1/4096 fIN. All inputs are equipped with protection circuits against static discharge and transient excess voltage.

PIN CONNECTION

May 2004

Rev. 1

1/11