M54HC4075| Datasheet

M54HC4075, M54HC4075K

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M54HC4075
RAD-HARD TRIPLE 3-INPUT OR GATE
s

s s

HIGH SPEED: tPD = 9 ns (TYP.) at VCC = 6V LOW POWER DISSIPATION: ICC = 1uA(MAX.) at TA=25 C HIGH NOISE IMMUNITY: VNIH = VNIL = 28% VCC (MIN.) SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 4mA (MIN) BALANCED PROPAGATION DELAYS: tPLH tPHL WIDE OPERATING VOLTAGE RANGE: VCC (OPR) = 2V to 6V PIN AND FUNCTION COMPATIBLE WITH 54 SERIES 4075 SPACE GRADE-1: ESA SCC QUALIFIED 50 krad QUALIFIED, 100 krad AVAILABLE ON REQUEST NO SEL UNDER HIGH LET HEAVY IONS IRRADIATION DEVICE FULLY COMPLIANT WITH SCC-9201-129

DILC-14

FPC-14

ORDER CODES
PACKAGE DILC FPC FM M54HC4075D M54HC4075K EM M54HC4075D1 M54HC4075K1

The internal circuit is composed of 4 stages including buffer output, which enables high noise immunity and stable output. All inputs are equipped with protection circuits against static discharge and transient excess voltage.

DESCRIPTION The M54HC4075 is an high speed CMOS TRIPLE 3-INPUT OR GATE fabricated with silicon gate C2MOS technology.

PIN CONNECTION

May 2004

Rev. 1

1/9