M54HC4514| Datasheet

M54HC4514, M54HC4514D, M54HC4514K, M54HC4514K1

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M54HC4514
RAD-HARD 4 TO 16 LINE DECODER/LATCH
s

s s

HIGH SPEED: tPD= 20 ns (TYP.) at VCC = 6V LOW POWER DISSIPATION: ICC = 4uA(MAX.) at TA=25 C HIGH NOISE IMMUNITY: VNIH = VNIL = 28% VCC (MIN.) SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 4mA (MIN) BALANCED PROPAGATION DELAYS: tPLH tPHL WIDE OPERATING VOLTAGE RANGE: VCC (OPR) = 2V to 6V PIN AND FUNCTION COMPATIBLE WITH 54 SERIES 4514 SPACE GRADE-1: ESA SCC QUALIFIED 50 krad QUALIFIED, 100 krad AVAILABLE ON REQUEST NO SEL UNDER HIGH LET HEAVY IONS IRRADIATION DEVICE FULLY COMPLIANT WITH SCC-9205-019

DILC-24

FPC-24

ORDER CODES
PACKAGE DILC FPC FM M54HC4514D M54HC4514K EM M54HC4514D1 M54HC4514K1

DESCRIPTION The M54HC4514 is an high speed CMOS 4 LINE TO 16 LINE SEGMENT DECODER WITH LATCHED INPUTS fabricated with silicon gate C2MOS technology. A binary code stored in the four input latches (A to D) provides a high level at the selected one of PIN CONNECTION

sixteen outputs excluding the other fifteen outputs, when the inhibit input (INHIBIT) is held low. When the inhibit input (INHIBIT) is held high, all outputs are kept low level, while the latch function is available. The data applied to the data inputs are transferred to the Q outputs of latches when the strobe input is held high. When the strobe input is taken low, the information data applied to the data input at a time is retained at the output of the latches. All inputs are equipped with protection circuits against static discharge and transient excess voltage.

May 2004

Rev. 1

1/10