M54HC590| Datasheet

M54HC590, M54HC590D, M54HC590K

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M54HC590
RAD-HARD 8 BINARY COUNTER REGISTER WITH 3 STATE OUTPUT
s

s s

HIGH SPEED: fMAX = 61 MHz (TYP.) at VCC = 6V LOW POWER DISSIPATION: ICC = 4uA(MAX.) at TA=25 C HIGH NOISE IMMUNITY: VNIH = VNIL = 28% VCC (MIN.) SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 6mA (MIN) for QA ~ QH OUTPUT |IOH| = IOL = 4mA (MIN) for RCO OUTPUT BALANCED PROPAGATION DELAYS: tPLH tPHL WIDE OPERATING VOLTAGE RANGE: VCC (OPR) = 2V to 6V PIN AND FUNCTION COMPATIBLE WITH 54 SERIES 590 SPACE GRADE-1: ESA SCC QUALIFIED 50 krad QUALIFIED, 100 krad AVAILABLE ON REQUEST NO SEL UNDER HIGH LET HEAVY IONS IRRADIATION DEVICE FULLY COMPLIANT WITH SCC-9204-071

DILC-16

FPC-16

ORDER CODES
PACKAGE DILC FPC FM M54HC590D M54HC590K EM M54HC590D1 M54HC590K1

DESCRIPTION The M54HC590 is an high speed CMOS 8-BIT BINARY COUNTER REGISTER (3 STATE) fabricated with silicon gate C2MOS technology. This device contains an 8-bit binary counter that feeds an 8-bit storage register. The storage

register has parallel outputs. Separate clocks are provided for both the binary counter and storage register. The binary counter features a direct clear input CCLR and a count enable input CCKEN. For cascading, a ripple carry output RCO is provided. Expansion is easily accomplished by tying RCO of the first stage to CCKEN of the second stage, etc. Both the counter and register clocks are positive edge triggered. If the user wishes to connect both clocks together, the counter state will always be one count ahead of the register. Internal circuitry prevents clocking from the clock enable. All inputs are equipped with protection circuits against static discharge and transient excess voltage.

PIN CONNECTION

June 2004

Rev. 1

1/16