M54HC597| Datasheet

M54HC597, M54HC597K

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M54HC597
RAD-HARD 8 BIT LATCH/SHIFT REGISTER
s

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HIGH SPEED: fMAX = 50 MHz (TYP.) at VCC = 6V LOW POWER DISSIPATION: ICC =4uA(MAX.) at TA=25 C HIGH NOISE IMMUNITY: VNIH = VNIL = 28% VCC (MIN.) SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 4mA (MIN) BALANCED PROPAGATION DELAYS: tPLH tPHL WIDE OPERATING VOLTAGE RANGE: VCC (OPR) = 2V to 6V PIN AND FUNCTION COMPATIBLE WITH 54 SERIES 597 SPACE GRADE-1: ESA SCC QUALIFIED 50 krad QUALIFIED, 100 krad AVAILABLE ON REQUEST NO SEL UNDER HIGH LET HEAVY IONS IRRADIATION DEVICE FULLY COMPLIANT WITH SCC-9306-054

DILC-16

FPC-16

ORDER CODES
PACKAGE DILC FPC FM M54HC597D M54HC597K EM M54HC597D1 M54HC597K1

DESCRIPTION The M54HC597 is an high speed CMOS 8 BIT PIPO SHIFT REGISTER fabricated with silicon gate C2MOS technology.

This devices comes in a 16-pin package and consist of an 8-bit storage latch feeding a parallel in, serial out 8-bit shift register. Both the storage register and shift register have positive edge triggered clocks. The shift register also has direct load (from storage) and clear inputs. All inputs are equipped with protection circuits against static discharge and transient excess voltage.

PIN CONNECTION

June 2004

Rev. 1

1/14