M54HC74| Datasheet

M54HC74, M54HC74D, M54HC74K, M54HC74K1

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M54HC74
RAD HARD DUAL D TYPE FLIP FLOP WITH PRESET AND CLEAR
s

s s

HIGH SPEED: fMAX = 67MHz (TYP.) at VCC = 6V LOW POWER DISSIPATION: ICC =2uA(MAX.) at TA=25 C HIGH NOISE IMMUNITY: VNIH = VNIL = 28% VCC (MIN.) SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 4mA (MIN) BALANCED PROPAGATION DELAYS: tPLH tPHL WIDE OPERATING VOLTAGE RANGE: VCC (OPR) = 2V to 6V PIN AND FUNCTION COMPATIBLE WITH 54 SERIES 74 SPACE GRADE-1: ESA SCC QUALIFIED 50 krad QUALIFIED, 100 krad AVAILABLE ON REQUEST NO SEL UNDER HIGH LET HEAVY IONS IRRADIATION DEVICE FULLY COMPLIANT WITH SCC-9203-050

DILC-14

FPC-14

ORDER CODES
PACKAGE DILC FPC FM M54HC74D M54HC74K EM M54HC74D1 M54HC74K1

DESCRIPTION The M54HC74 is an high speed CMOS DUAL D TYPE FLIP FLOP WITH CLEAR fabricated with silicon gate C2MOS technology.

A signal on the D INPUT is transferred on the Q OUTPUT during the positive going transition of the clock pulse. CLEAR and PRESET are independent of the clock and accomplished by a low on the appropriate input. All inputs are equipped with protection circuits against static discharge and transient excess voltage.

PIN CONNECTION

June 2004

Rev. 1

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