M74HC623| Datasheet

M74HC623, M74HC623B1R

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M74HC623
OCTAL BUS TRANSCEIVER WITH 3 STATE OUTPUTS (NON INVERTING)
s

HIGH SPEED: tPD = 10ns (TYP.) at VCC = 6V LOW POWER DISSIPATION: ICC = 4uA(MAX.) at TA=25 C HIGH NOISE IMMUNITY: VNIH = V NIL = 28 % VCC (MIN.) SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 6mA (MIN) BALANCED PROPAGATION DELAYS: tPLH tPHL WIDE OPERATING VOLTAGE RANGE: VCC (OPR) = 2V to 6V PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 623

DIP

SOP

TSSOP

ORDER CODES
PACKAGE DIP SOP TSSOP TUBE M74HC623B1R M74HC623M1R T&R M74HC623RM13TR M74HC623TTR

DESCRIPTION The 74HC623 is an advanced high-speed CMOS OCTAL BUS TRANSCEIVER (3-STATE) fabricated with silicon gate technology. This IC is intended for two-way asynchronous communication between data buses. The control function implementation allows maximum flexibility in timing. This device allows data transmission from the A bus to B bus or from the B to the A bus depending upon the logic level levels at the enable inputs (GBA and GAB). The enable inputs can be used to disable the device so that the buses are effectively isolated. The dual enable configuration gives this

device the capability to store data by simultaneous enabling of GBA and GAB. Each output reinforces its input in this transceiver configuration. Thus, when both control inputs are enabled and all other data sources to the two sets of bus lines are at high impedance, both sets of bus lines (16 in all) will remain at their last states. The 8-bit codes appearing on the two sets of buses will be identical. All inputs are equipped with protection circuits against static discharge and transient excess voltage.

PIN CONNECTION AND IEC LOGIC SYMBOLS

August 2001

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