M74HC73| Datasheet

M74HC73, M74HC73B1R, M74HC73RM13TR, M74HC73TTR

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M74HC73
DUAL J-K FLIP FLOP WITH PRESET AND CLEAR
s

HIGH SPEED : fMAX = 80MHz (TYP.) at VCC = 6V LOW POWER DISSIPATION: ICC =2uA(MAX.) at TA=25 C HIGH NOISE IMMUNITY: VNIH = V NIL = 28 % VCC (MIN.) SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 4mA (MIN) BALANCED PROPAGATION DELAYS: tPLH tPHL WIDE OPERATING VOLTAGE RANGE: VCC (OPR) = 2V to 6V PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 73

DIP

SOP

TSSOP

ORDER CODES
PACKAGE DIP SOP TSSOP TUBE M74HC73B1R M74HC73M1R T&R M74HC73RM13TR M74HC73TTR

DESCRIPTION The M74HC73 is an high speed CMOS DUAL J-K FLIP FLOP WITH CLEAR fabricated with silicon gate C2MOS technology. Depending on the logic level applied to J and K inputs, this device changes state on the negative going transition of clock input pulse (CK). The

clear function is accomplished independently of the clock condition when the clear input (CLR) is taken low. All inputs are equipped with protection circuits against static discharge and transient excess voltage.

PIN CONNECTION AND IEC LOGIC SYMBOLS

August 2001

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