M74HC75| Datasheet

M74HC75, M74HC75RM13TR, M74HC75TTR

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M74HC75
4 BIT D TYPE LATCH
s

HIGH SPEED : tPD = 11ns (TYP.) at VCC = 6V LOW POWER DISSIPATION: ICC =2uA(MAX.) at TA=25 C HIGH NOISE IMMUNITY: VNIH = V NIL = 28 % VCC (MIN.) SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 4mA (MIN) BALANCED PROPAGATION DELAYS: tPLH tPHL WIDE OPERATING VOLTAGE RANGE: VCC (OPR) = 2V to 6V PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 75

DIP

SOP

TSSOP

ORDER CODES
PACKAGE DIP SOP TSSOP TUBE M74HC75B1R M74HC75M1R T&R M74HC75RM13TR M74HC75TTR

DESCRIPTION The M74HC75 is an high speed CMOS 4 BIT D TYPE LATCH fabricated with silicon gate C2MOS technology. It contains two groups of 2 bit latches controlled by an enable input (G1 2 or G3 4). These two latch groups can be used in different circuits. Each latch has Q and Q outputs (1Q - 4Q and 1Q - 4Q). The data applied to the data input is transferred to the

Q and Q outputs when the enable input is taken high and the outputs will follow the data input as long as the enable input is kept high. When the enable input is taken low, the information data applied to the data input is retained at the outputs. All inputs are equipped with protection circuits against static discharge and transient excess voltage.

PIN CONNECTION AND IEC LOGIC SYMBOLS

August 2001

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