M74HCT373| Datasheet

M74HCT373, M74HCT373B1R, M74HCT373RM13TR, M74HCT373TTR

Datasheet preview, take a look at Datasheets before downloading (Data Sheet is available on manufacturer site)

M74HCT373
OCTAL D-TYPE LATCH WITH 3 STATE OUTPUT NON INVERTING
s

HIGH SPEED: tPD = 19ns (TYP.) at VCC = 4.5V LOW POWER DISSIPATION: ICC = 4uA(MAX.) at TA=25 C COMPATIBLE WITH TTL OUTPUTS : VIH = 2V (MIN.) VIL = 0.8V (MAX) SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 6mA (MIN) BALANCED PROPAGATION DELAYS: tPLH tPHL PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 373

DIP

SOP

TSSOP

ORDER CODES
PACKAGE DIP SOP TSSOP TUBE M74HCT373B1R M74HCT373M1R T&R M74HCT373RM13TR M74HCT373TTR

DESCRIPTION The M74HCT373 is an high speed CMOS OCTAL LATCH WITH 3-STATE OUTPUTS fabricated with sub-micron silicon gate C2MOS technology. This 8-BIT D-Type latches is controlled by a latch enable input (LE) and output enable input (OE). While the LE input is held at a high level, the Q outputs will follow the data input. When the LE is taken low, the Q outputs will be latched at the logic level of D input data. While the OE input is at low level, the eight outputs will be in a normal logic state (high or low logic

level) and when OE is in high level the outputs will be in a high impedance state. The 3-State output configuration and the wide choice of outline make bus organized system simple. All inputs are equipped with protection circuits against static discharge and transient excess voltage.

PIN CONNECTION AND IEC LOGIC SYMBOLS

August 2001

1/11