M74HCT652| Datasheet

M74HCT652, M74HCT652RM13TR

Datasheet preview, take a look at Datasheets before downloading (Data Sheet is available on manufacturer site)

M74HCT652
OCTAL BUS TRANSCEIVER/REGISTER WITH 3 STATE OUTPUTS
s

HIGH SPEED: fMAX = 55 MHz (TYP.) at VCC = 4.5V LOW POWER DISSIPATION: ICC = 4uA(MAX.) at TA=25 C COMPATIBLE WITH TTL OUTPUTS : VIH = 2V (MIN.) VIL = 0.8V (MAX) SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 6mA (MIN) BALANCED PROPAGATION DELAYS: tPLH tPHL PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 652

DIP

SOP

TSSOP

ORDER CODES
PACKAGE DIP SOP TSSOP TUBE M74HCT652B1R M74HCT652M1R T&R M74HCT652RM13TR M74HCT652TTR

DESCRIPTION The 74HCT652 is an advanced high-speed CMOS OCTAL BUS TRANSCEIVER AND REGISTER (3-STATE) fabricated with silicon gate C2MOS technology. This device consists of bus transceiver circuits, D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the input bus or from the internal storage registers. Enable GAB and GBA are provided to control the transceiver functions. Select AB(SAB) and select BA(SBA) control pins are provided to select whether real-time or stored data is transferred. A low input level selects real-time data, and a high selects stored data. Data on the A or B bus, or both, can be stored in the internal D flip-flops by low-to-high transition at the appropriate clock pins (CLOCK AB or CLOCK PIN CONNECTION AND IEC LOGIC SYMBOLS

BA) regardless of the select or enable control pins. When select AB and select BA are in the real time transfer mode, it is also possible to store data without using the internal D type flip-flops by simultaneously enabling GAB and GBA. In this configuration each output reinforces its input. Thus, when all other data sources to the two sets of bus lines are at high impedance, each set of bus lines will remain at its last state. All inputs are equipped with protection circuits against static discharge and transient excess voltage.

April 2003

1/15