M74HCT7259| Datasheet

M74HCT7259, M74HCT7259RM13TR

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M74HCT7259
8 BIT ADDRESSABLE LATCH/DECODER/RELAIS DRIVER OPEN DRAIN, INVERTING OUTPUT
s

LOW POWER DISSIPATION: ICC =4uA(MAX.) at TA=25 C COMPATIBLE WITH TTL OUTPUTS : VIH = 2V (MIN.) VIL = 0.8V (MAX) HIGH CURRENT OPEN DRAIN OUTPUT UP TO 80 mA
DIP SOP TSSOP

DESCRIPTION The M74HCT7259 is an high speed CMOS 8 BIT ADDRESSABLE LATCH/DECODER fabricated with silicon gate C2MOS technology. This device has single data input (D) 8 LATCH inverted OUTPUTS (Q0 - Q7), 3 address inputs (A, B and C), common enable input (ENABLE) and a common CLEAR input. To operate this device as an addressable latch, data is held on the D input, and the address of the latch into which the data is to be entered is held on the A, B and C inputs. When ENABLE is taken low the data flows through to the address output. The data is stored on the positive going edge of the ENABLE pulse. All unaddressed latches will remain unaffected. With ENABLE in the high state the device is deselected and all latches remain in their previous state, unaffected by changes on the data or address inputs. To eliminate the possibility of entering erroneous data into the latches, the ENABLE should be held high (inactive) while the address lines are changing. If ENABLE is held

ORDER CODES
PACK. DIP SOP TSSOP TUBE T&R M74HCT7259B1R M74HCT7259M1R M74HCT7259RM13TR M74HCT7259TTR

high and CLEAR is taken low all eight latches are cleared to the HIGH (OFF) state. If ENABLE is low all latches except the addressed latch will be cleared. The address latch will instead be the complement of the D input, effectively implementing a 3 to 8 line decoder. Internal clamp diodes protect the open drain outputs against over voltages due to inductive loads. All inputs are equipped with protection circuits against static discharge and transient excess voltage.

PIN CONNECTION AND IEC LOGIC SYMBOLS

September 2001

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