SPEAR-09-P022| Datasheet

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SPEAR-09-P022
SPEArTM Plus600 dual processor cores
Preliminary Data

Features

Dual ARM926EJ-S core @333MHz. 600KByte reconfigurable logic array with 88 dedicated General purposes I/Os, 9 LVDS channels and 128KByte configurable internal memory pool. Multilayer AMBA 2.0 compliant Bus with fMAX 166MHz 32KByte Rom. 8KByte common Static Ram. Dynamic Power saving features. High performance 8 channels DMA. Ethernet 10/100/1000 MAC with GMII/MII Interface to external PHY. USB2.0 device with integrated PHY. 2 USB2.0 Host with integrated PHY. Ext. SDRAM memory interface: 8/16bit (DDR1@200MHz) 8/16bit (DDR2@333MHz) Flashes interface: Nand 8/16bit Serial (up to 50Mbps). 3-SPI Master/Slave up to 40Mbps. I2C Master/Slave mode - High, Fast and Slow speed. 2 independent UART up to 460.8 Kbps with Software Flow Control mode. IrDA (Fir-Mir-Sir) from 9.6Kbps to 4Mbps speed-rate. Colour LCD controller: up to 1024x768 resolutions. Device summary
Op. temp. range, C -40 to 85 Package PBGA420(23x23x1.81mm) Packing Tray

PBGA420

24bpp true colour TFT panel. 16bpp DSTN panel. 10 GPIOs bidirectional signals with interrupt capability. 88 RAS-GPIOs user customizable bidirectional signals (up to 4 clocks). ADC 10 bit, 1MSPS, 8 analog inputs. JPEG codec accelerator. 10 independent Timers with programmable prescaler. Real Time Clock. WatchDog System Controller MISC internal control registers. JTAG (IEEE1149.1) interface

Description
SPEAr Plus600 is a powerful digital engine belonging to SPEAr family, the innovative customizable System on chip. The device integrates two ARM 926 cores with a large set of proven IPs and a big configurable logic block that allow very fast customization of unique and/or proprietary solution.

Table 1.

Part number SPEAR-09-P022

February 2007

Rev 1

1/37
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This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.