ST10R172L| Datasheet

ST10R172L, ST10R172LT1, ST10R172LT6

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ST10R172L
16-BIT LOW VOLTAGE ROMLESS MCU
DATASHEET
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High Performance 16-bit CPU
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CPU Frequency: 0 to 50 MHz 40ns instruction cycle time at 50-MHz CPU clock 4-stage pipeline Register-based design with multiple variable register banks Enhanced boolean bit manipulation facilities Additional instructions to support HLL and operating systems Single-cycle context switching support 1024 bytes on-Chip special function register area 1KByte on-chip RAM Up to 16 MBytes linear address space for code and data (1 MByte with SSP used) Programmable external bus characteristics for different address ranges 8-bit or 16-bit external data bus Multiplexed or demultiplexed external address/data buses Five programmable chip-select signals Hold and hold-acknowledge bus arbitration support

Dedicated pins O SC

P.6

P.4 XSSP

P.1

P.0

W DT PLL

ST10 CO RE DPRAM Interrupt Controller &PEC ASC P.3 GPT1/2 P.5 PW M P.7 Po.2

Memory Organisation
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External Memory Interface
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Two multi-functional general purpose timer units with 5 timers Clock Generation via on-chip PLL, or via direct or prescaled clock input Synchronous/asynchronous High-speed-synchronous serial port SSP

Serial Channels
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Up to 77 general purpose I/O lines No bootstrap loader Electrical Characteristics
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One Channel PWM Unit Fail Safe Protection
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Programmable watchdog timer Oscillator Watchdog
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5V Tolerant I/Os 5V Fail-Safe Inputs (Port 5) Power: 3.3 Volt +/-0.3V Idle and power down modes C-compilers, macro-assembler packages, emulators, evaluation boards, HLLdebuggers, simulators, logic analyser disassemblers, programming boards 100-Pin Thin Quad Flat Pack (TQFP) Rev. 1.2

Interrupt
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Support
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8-channel interrupt-driven single-cycle data transfer facilities via peripheral event controller (PEC) 16-priority-level interrupt system with 17 sources, sample-rate down to 40 ns

Timers

Package
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March 2001

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