ST140| Datasheet

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ST140
ST140 DSP CORE
DATA BRIEF

FEATURES Advanced Load/store Architecture Regular and efficient. Optimized for programming in `C/C++/EC++' languages. Two Instruction Sets GP16, a 16-bit instruction set. GP32, a 32-bit instruction set. Three Instruction Modes GP16: 2-way superscalar, for compact microcontroller codes. GP32: 2-way superscalar, for high performance microcontroller codes. SLIW: one SLIW per cycle, where a SLIW (Scoreboarded Long Instruction Word), is a bundle of four GP32 instruction words. This mode is for high performance vector codes (DSP loops). At the instruction-set level, the ST122 is forward-binary compatible with the ST140 Predicated Execution For Most Instructions Removes needs of conditional branches. Compact coding and increased instruction level parallelism. Flexible Data Format The ST140 supports the following data types: 16-bit, 32-bit and 40-bit unsigned/signed integer. 16-bit, 32-bit, and 40-bit signed fractional. Signed and unsigned byte. Supports little Endian for data and progr
am. Circular And Bit-reversed DSP Addressing Modes Facilitates the implementation of the DSP algorithms like the FIR filters and the FFT. Arithmetic Capability 40-bit and 32-bit arithmetic. Packed Arithmetic 2 x 16-bit (SIMD). Saturating (Clamping) and/or Rounding options Two Data Units providing four MAC's, four Barrel Shifters, four ALU's, four Saturations Units

Application Oriented Instructions Useful instructions for ETSI (European Telecommunications Standards Institute) primitives in GP32 and GP16: NORMW, Half-Word CLAMP, SHLCW, VITERBI... General usage instructions: Minimum/Maximum, absolute value,/de-interleave. Instructions for multi-precision filters/FFT (32*16 bits Multiply, Multiply -Accumulate/ subtract). SIMD Multiple Data Clusters Supporting vectors of basic data types. Same instructions executed in different data clusters like a SIMD style. Programmable data operation mode selection: single or multiple cluster operation modes. Instructions defined for inter-cluster data exchanges. Hardware Loop Controllers Zero cycles overhead for continuous data processing. Three nestable loops. Memory Space One 128-bit Program bus and two 64-bit data buses (X and Y). 32-bit addressing range, 4 Gbytes of memory space. Flexible memory space. Interrupt, Trap And Context Switching Fast response to external events or system errors. 32 Interrup
t (5-bit) levels. Software interrupts allowed by writing to the interrupt controller register. Protection System User mode and Supervisor mode. Power Saving Four "IDLE" modes performing power saving operations. The Program cache also implements a low consumption mode.
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May 2004