STA240| Datasheet

STA240, STA240A

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STA240
Sirius SDARS channel, service & source decoder
Data Brief

Features

2 Satellite and 1 terrestrial signal demodulators and decoders Advanced DSP processor to implement PAC audio decoder Requires a single 17MHz clock reference; all high-speed clock signals are derived using on-chip PLL Programmable I2S to support 32K/48K/44.1K audio sample rate (32K/48K Sample rates use internal clocks, 44.1K Sample rate uses external clock) I2C master interface to control tuner and audio DAC External control through uart interface using sirius standard protocol (SSP) over RS-232
LBGA288

Description
STA240 is a fully integrated 3rd generation Baseband signal processor for Sirius Satellite Digital Radio Service (SDARS). It is implemented using ST Micro's advanced 0.13um HCMOS9 technology. It allows a highly efficient implementation of a Sirius "SDARS Satellite Digital Audio Radio Service" receiver when used with its companion STA210 tuner ASIC. STA240 is packaged in a low profile BGA (LBGA 19x19)

Analog to digital converters

Three internal 10 BIT A/D converters for 76.5MHZ if signals conversion

Low power technology

1.2V, 0.13 um technology 3.3V capable I/OS

Table 1.

Device summary
Part Number STA240 Package LBGA288 Packing Tray

June 2007

Rev 1

1/6
www.st.com 6

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