STI1000ZWA, STI1000ZWB, STi1000

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STi1000
Single-chip worldwide iDTV processor
Data Brief

Features
The STi1000 is a single-chip worldwide iDTV Processor that includes:

32-Bit RISC ST40 CPU, 266 MHz, 480 MIPs DDR2 unified memory interface, 250 MHz clock Transport stream demultiplexer with DES, DVB and Multi2 descrambler CableCard and DVB-CI interface MP@ML and MP@HL MPEG-2 video decoder 24-bit audio DSP core, MPEG-1(layers 1,2,3), MPEG-2, MPEG-2-AAC, Dolby Digital, MP3 decoder Analog video input: CVBS, SVHS(Y/C), Component (from SD up to HD 720p, 1080i, 1080p) PC input, analog RGB up to UXGA/60 Hz (162 MHz sampling frequency) 24-bit digital video input, up to 1080p and UXGA/60 Hz
PC H/V syncs DATA(32-bit) ADDR PC_R/Pr2 PC_B/Pb2 PC_G/Y2 CVBS1 G1/Y1 B1/Pb1 R1/C1/Pr1 FB CEC/HPD DDC HDMI

HDMI/HDCP input, RGB/YCrCb up to 1080p, UXGA/60 Hz, support stereo and 5.1 multi-channel audio. Compliant with HDMI 1.3, DVI 1.0, HDCP v1.1 USB2.0 high speed interface (480 Mbits/s) High definition video processor Multi-standard color decoder (PAL/SECAM/NTSC), with 3D comb filtering in NTSC and PAL, Luma and Chroma spatio-temporal (3D) noise reduction Double video pipe for Picture In Picture (PIP) display 2D graphic accelerator and enhanced true color on screen display. Bitmap OSD generated at panel resolution Video and graphic composition for Picture And Text (PAT), Picture And Graphic (PAG), mosaic Exhaustive set of peripherals for DTV chassis control Flat panel display video output, up to 1920 x 1080p resolution.
24 MHz XTAL PWM GP I/O Interrupts ADC input
Text/CC VBI denc DENC

DATA(16-bit) ADDR

Test Port

USB 2.0

MUX D1/HD HD/D1 in HD H/V syncs 24/16/8-bit digital in. ADC ADC ADC ADC Digital Decoder 3D Comb 3D-NR HDMI/ HDCP input

PIOs System USB2.0 Clock ST40 EMI HOST Mgt CPU External Chassis Control JTAG 266 MHz, VTG Memory Advance Interface 480 MIPs (IT, WDG, RTC, ADC, IR, main 16K-I User NAND/NOR PWM, UARTs, I2C...) and aux DDR2-500 32K-D Flash Debug LMI Local Memory Interface

STi1000

ST Bus On-Chip Interconnect

MPEG-2 Video Decoder (SD / HD) TSin

GFx 2D GFx accelerator planes (x2)

Main Video pipe FMD/DEi H/V SRC IQI

Secondary Video pipe DEi-light H/V SRC Aux Compo.

Aux Video*

TS Processing CA Interfaces

Audio Decoder (DSP) MPEG-1, MPEG-2, MP3 Dolby Digital, AAC

Main Compositor

Gamma, Color warping, PCE DAC DAC DAC

CK, DE, GFx

SPDIF out 4x I S_out

30-bits RBG out

H/V syncs

CA in

I2S_ in

CA out

UART

Reset

I C

* Secondary video pipe and auxiliary video output are exclusive

October 2007

Rev 1

CVBS/YC

1/5
www.st.com 5

For further information contact your local STMicroelectronics sales office.

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STI1000ZWA DATASHEET