STLS2E02| Datasheet

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STLS2E02
Loongson 2E: 700MHz 64-bit superscalar MIPS based microprocessor
Data Brief

Features

64 bit superscalar architecture 700MHz clock frequency (typical conditions) Single/double precision floating-point units New Streaming Multimedia instruction set support (SIMD) 64KB instruction cache, 64KB data cache, onchip 512KB unified L2 cache On-chip DDR-333 controller Thermal Design Power (TDP) 4W @ 700MHz Leading edge 90nm process technology 35x35 BGA package MIPS based MIPS bus interface (Sysad) The memory hierarchy is composed by the first level of 64KB 4-way set associative cache for instructions and data, the second level of 512KB unified 4-ways set associative cache and the Memory Management Unit with Table Lookside Buffer. The Loongson microprocessor family is the outcome of a successful collaboration started in 2004 between STMicroelectronics and the Institute of Computing Technology, part of the Chinese Academy of Science. Loongson microprocessors were co-developed by STMicroelectronics and the Institute of Computing Technology to address all the applications requiring high level of performa
nce and low power dissipation.
PBGA452

Description
The STLS2E02, is a MIPS based 64-bit superscalar microprocessor, able to issue four instructions per clock cycle among six functional units: two integer, two single/double-precision floating-point, one 64bit SIMD and one load/store unit. The microarchitecture is organized with nine stages of pipeline and support of dynamic branch prediction. Table 1. Device summary
Part numbers STLS2E02

Package PBGA452 (35x35x2.33mm)

Packing Tray

April 2007

Rev 2

1/5
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