STP40NS15| Datasheet

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STP40NS15
N-CHANNEL 150V - 0.042 - 40A TO-220 MESH OVERLAYTM MOSFET
PRELIMINARY DATA TYPE STP40NS15
s s s s

VDSS 150 V

RDS(on) <0.052

ID 40A

TYPICAL RDS(on) = 0.042 EXTREMELY HIGH dv/dt CAPABILITY VERY LOW INTRINSIC CAPACITANCES GATE CHARGE MINIMIZED
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DESCRIPTION This powermos MOSFET is designed using the company's consolidated strip layout-based MESH OVERLAYTM process. This technology matches and improves the performances compared with standard parts from various sources.

TO-220

INTERNAL SCHEMATIC DIAGRAM APPLICATIONS s HIGH CURRENT SWITCHING s UNINTERRUPTIBLE POWER SUPPLY (UPS) s PRIMARYSWITCH IN ISOLATED DC-DC CONVERTERS

ABSOLUTE MAXIMUM RATINGS
Symbol VDS VDGR VGS ID ID IDM (q ) PTOT dv/dt Tstg Tj Parameter Drain-source Voltage (VGS = 0) Drain-gate Voltage (RGS = 20 k) Gate- source Voltage Drain Current (continuos) at TC = 25 C Drain Current (continuos) at TC = 100 C Drain Current (pulsed) Total Dissipation at TC = 25 C Derating Factor Peak Diode Recovery voltage slope Storage Temperature Max. Operating Junction Temperature Value 150 150 20 40 25 160 140 0.933 9 65 to 175 175 Unit V V V A A A W W/ C V/ns C C

( )Pulse width limited by safe operating area

October 2000
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

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