74AUC08-0_8V| Datasheet

74AUC08-0_8V, 74AUC08-1_2V, 74AUC08-1_5V, 74AUC08-1_8V, 74AUC08-2_5

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SN74AUC08 QUADRUPLE 2-INPUT POSITIVE-AND GATE
SCES512A NOVEMBER 2003 REVISED MARCH 2005

FEATURES
Optimized for 1.8-V Operation and Is 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation Ioff Supports Partial-Power-Down Mode Operation Sub-1-V Operable Max tpd of 1.9 ns at 1.8 V Low Power Consumption, 10-uA Max ICC 8-mA Output Drive at 1.8 V Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II ESD Protection Exceeds JESD 22 2000-V Human-Body Model (A114-A) 200-V Machine Model (A115-A) 1000-V Charged-Device Model (C101)

RGY PACKAGE (TOP VIEW)

14 13 4B 12 4A 11 4Y 10 3B 9 3A

1B 1Y 2A 2B 2Y

2 3 4 5 6 7 8

DESCRIPTION/ORDERING INFORMATION
This quadruple 2-input positive-AND gate is operational at 0.8-V to 2.7-V VCC, but is designed specifically for 1.65-V to 1.95-V VCC operation. The SN74AUC08 device performs the Boolean function Y + A B or Y + A ) B in positive logic. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. ORDERING INFORMATION
TA 40 C to 85 C (1) QFN RGY PACKAGE (1) Tape and reel ORDERABLE PART NUMBER SN74AUC08RGYR TOP-SIDE MARKING MS08

Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package.

FUNCTION TABLE (EACH GATE)
INPUTS A H L X B H X L OUTPUT Y H L L

LOGIC DIAGRAM, EACH GATE (POSITIVE LOGIC)
A B Y

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

GND

VCC