CD74ACT161| Datasheet

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CD54ACT161, CD74ACT161 4-BIT SYNCHRONOUS BINARY COUNTERS
SCHS298B APRIL 2000 REVISED MARCH 2003

D D D D D D D

Inputs Are TTL-Voltage Compatible Internal Look-Ahead for Fast Counting Carry Output for n-Bit Cascading Synchronous Counting Synchronously Programmable SCR-Latchup-Resistant CMOS Process and Circuit Design Exceeds 2-kV ESD Protection per MIL-STD-883, Method 3015

CD54ACT161 . . . F PACKAGE CD74ACT161 . . . E OR M PACKAGE (TOP VIEW)

description/ordering information

CLR CLK A B C D ENP GND

1 2 3 4 5 6 7 8

16 15 14 13 12 11 10 9

VCC RCO QA QB QC QD ENT LOAD

The 'ACT161 devices are 4-bit binary counters. These synchronous, presettable counters feature an internal carry look-ahead for application in high-speed counting designs. Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs change coincident with each other when so instructed by the count-enable (ENP, ENT) inputs and internal gating. This mode of operation eliminates the output counting spikes that normally are associated with synchronous (ripple-clock) counters. A buffered clock (CLK) input triggers the four flip-flops on the rising (positive-going) edge of the clock waveform. These devices are fully programmable; that is, they can be preset to any number between 0 and 9 or 15. Presetting is synchronous; therefore, setting up a low level at the load input disables the counter and causes the outputs to agree with the setup data after the next clock pulse, regardless of the levels of the enable inputs. The clear function is asynchronous. A low level at the cle
ar (CLR) input sets all four of the flip-flop outputs low, regardless of the levels of the CLK, load (LOAD), or enable inputs. The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications without additional gating. Instrumental in accomplishing this function are ENP, ENT, and a ripple-carry output (RCO). Both ENP and ENT must be high to count, and ENT is fed forward to enable RCO. Enabling RCO produces a high-level pulse while the count is maximum (9 or 15, with QA high). This high-level overflow ripple-carry pulse can be used to enable successive cascaded stages. Transitions at ENP or ENT are allowed, regardless of the level of CLK. The counters feature a fully independent clock circuit. Changes at control inputs (ENP, ENT, or LOAD) that modify the operating mode have no effect on the contents of the counter until clocking occurs. The function of the counter (whether enabled, disabled, loading, or counting) is dictated solely by the conditions meeting the stable setup an
d hold times. ORDERING INFORMATION
TA PACKAGE PDIP E 55 C to 125 C 55 C SOIC M CDIP F Tube Tube Tape and reel Tube ORDERABLE PART NUMBER CD74ACT161E CD74ACT161M CD74ACT161M96 CD54ACT161F3A TOP-SIDE MARKING CD74ACT161E ACT161M CD54ACT161F3A

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Copyright 2003, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

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