CD74HC4015| Datasheet

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CD54HC4015, CD74HC4015
Data sheet acquired from Harris Semiconductor SCHS198C

November 1997 - Revised May 2003

High Speed CMOS Logic Dual 4-Stage Static Shift Register
Description
The 'HC4015 consists of two identical, independent, 4-stage serial-input/parallel-output registers. Each register has independent Clock (CP) and Reset (MR) inputs as well as a single serial Data input. "Q" outputs are available from each of the four stages on both registers. All register stages are Dtype, master-slave flip-flops. The logic level present at the Data input is transferred into the first register stage and shifted over one stage at each positive- going clock transition. Resetting of all stages is accomplished by a high level on the reset line. The device can drive up to 10 low power Schottky equivalent loads. The 'HC4015 is an enhanced version of equivalent CMOS types.

Features [ /Title (CD74 HC401 5) /Subject (High Speed CMOS Logic Dual 4 Maximum Frequency, Typically 60MHz CL = 15pF, VCC = 5V, TA = 25oC Positive-Edge Clocking Overriding Reset Buffered Inputs and Outputs Fanout (Over Temperature Range) - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads Wide Operating Temperature Range . . . -55oC to 125oC Balanced Propagation Delay and Transition Times Significant Power Reduction Compared to LSTTL Logic ICs HC Types - 2V to 6V Operation - High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V

Ordering Information
PART NUMBER CD54HC4015F3A CD74HC4015E CD74HC4015M TEMP. RANGE (oC) -55 to 125 -55 to 125 -55 to 125 PACKAGE 16 Ld CERDIP 16 Ld PDIP 16 Ld SOIC

Pinout
CD54HC4015 (CERDIP) CD74HC4015 (PDIP, SOIC) TOP VIEW
2CP 1 2Q3 2 1Q2 3 1Q1 4 1Q0 5 1MR 6 1D 7 GND 8 16 VCC 15 2D 14 2MR 13 2Q0 12 2Q1 11 2Q2 10 1Q3 9 1CP

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright

2003, Texas Instruments Incorporated