CD74HC4094| Datasheet

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CD54HC4094, CD74HC4094, CD74HCT4094
Data sheet acquired from Harris Semiconductor SCHS211D

November 1997 - Revised October 2003

High-Speed CMOS Logic 8-Stage Shift and Store Bus Register, Three-State
Two serial outputs are available for cascading a number of these devices. Data is available at the QS1 serial output terminal on positive clock edges to allow for high-speed operation in cascaded system in which the clock rise time is fast. The same serial information, available at the QS2 terminal on the next negative clock edge, provides a means for cascading these devices when the clock rise time is slow.

Features
Buffered Inputs

[ /Title (CD74H C4094, CD74H CT4094 ) /Subject (High Speed CMOS Logic 8-

Separate Serial Outputs Synchronous to Both Positive and Negative Clock Edges For Cascading Fanout (Over Temperature Range) - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads Wide Operating Temperature Range . . . -55oC to 125oC Balanced Propagation Delay and Transition Times Significant Power Reduction Compared to LSTTL Logic ICs HC Types - 2V to 6V Operation - High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V HCT Types - 4.5V to 5.5V Operation - Direct LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH = 2V (Min) - CMOS Input Compatibility, Il 1uA at VOL, VOH

Ordering Information
PART NUMBER CD54HC4094F3A CD74HC4094E CD74HC4094M CD74HC4094MT CD74HC4094M96 CD74HC4094NSR CD74HC4094PW CD74HC4094PWR CD74HC4094PWT CD74HCT4094E CD74HCT4094M CD74HCT4094MT CD74HCT4094M96 TEMP. RANGE (oC) -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 PACKAGE 16 Ld CERDIP 16 Ld PDIP 16 Ld SOIC 16 Ld SOIC 16 Ld SOIC 16 Ld SOP 16 Ld TSSOP 16 Ld TSSOP 16 Ld TSSOP 16 Ld PDIP 16 Ld SOIC 16 Ld SOIC 16 Ld SOIC

Description
The 'HC4094 and CD74HCT4094 are 8-stage serial shift registers having a storage latch associated with each stage for strobing data from the serial input to parallel buffered three-state outputs. The parallel outputs may be connected directly to common bus lines. Data is shifted on positive clock transitions. The data in each shift register stage is transferred to the storage register when the Strobe input is high. Data in the storage register appears at the outputs whenever the Output-Enable signal is high.

NOTE: When ordering, use the entire part number. The suffixes 96 and R denote tape and reel. The suffix T denotes a small-quantity reel of 250.

Pinout
CD54HC4094 (CERDIP) CD74HC4094 (PDIP, SOIC, SOP, TSSOP) CD74HCT4094 (PDIP, SOIC) TOP VIEW
STROBE 1 DATA 2 CP 3 Q0 4 Q1 5 Q2 6 Q3 7 GND 8 16 VCC 15 OE 14 Q4 13 Q5 12 Q6 11 Q7 10 QS2 9 QS1

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright

2003, Texas Instruments Incorporated