CDCM1802| Datasheet

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CDCM1802 CLOCK BUFFER WITH PROGRAMMABLE DIVIDER, LVPECL I/O + ADDITIONAL LVCMOS OUTPUT
SCAS759 - APRIL 2004

D Distributes One Differential Clock Input to D D D D D

D D

One LVPECL Differential Clock Output and One LVCMOS Single-Ended Output Programmable Output Divider for Both LVPECL and LVCMOS Outputs 1.6-ns Output Skew Between LVCMOS and LVPECL Transitions Minimizing Noise 3.3-V Power Supply (2.5-V Functional) Signaling Rate Up to 800-MHz LVPECL and 200-MHz LVCMOS Differential Input Stage for Wide Common-Mode Range Also Provides VBB Bias Voltage Output for Single-Ended Input Signals Receiver Input Threshold 75 mV 16-Pin QFN Package (3 mm x 3 mm)

QFN PACKAGE (TOP VIEW)

Vss 14

VDDPECL IN IN VBB

1 2 3 4 5 6 7 8

13 12 11 10 9

VDD0 Y0 Y0 VDD0

Vss

description
The CDCM1802 clock driver distributes one pair of differential clock input to one LVPECL differential clock output pair Y0 and Y0 and one single-ended LVCMOS output Y1. It is specifically designed for driving 50- transmission lines. The LVCMOS output is delayed by 1.6 ns over the PECL output stage to minimize noise impact during signal transitions. The CDCM1802 has two control pins, S0 and S1, to select different output mode settings. The S[1:0] pins are 3-level inputs. Additionally, an enable pin EN is provided to disable or enable all outputs simultaneously. The CDCM1802 is characterized for operation from -40 C to 85 C. For single-ended driver applications, the CDCM1802 provides a VBB output pin that can be directly connected to the unused input as a common-mode voltage reference.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

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Vdd1