CDCVF25084| Datasheet

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CDCVF25084 3.3-V 1:8 ZERO DELAY (PLL) x4 CLOCK MULTIPLIER
SCAS690A APRIL 2003 REVISED MAY 2003

D Phase-Locked Loop-Based Multiplier by
Four

PW PACKAGE (TSSOP) (TOP VIEW)

D Input Frequency Range: 2.5 MHz to 45 MHz D Output Frequency Range: 10 MHz to D D D D D D D D D D
180 MHz LVCMOS/LVTTL I/O Compatible Low Jitter (Cycle-Cycle): 120 ps Over the Range 75 MHz to 180 MHz Distributes One Clock Input to Two Banks of Four Outputs Auto Frequency Detection to Disable Device (Power-Down Mode) Operates From Single 3.3-V Supply Industrial Temperature Range 40 C to 85 C 25- On-Chip Series Damping Resistors No External RC Network Required Spread Spectrum Clock Compatible (SSC) Available in 16-Pin TSSOP Package

CLKIN 1Y0 1Y1 VDD GND 2Y0 2Y1 S2

1 2 3 4 5 6 7 8

16 15 14 13 12 11 10 9

FBIN 1Y3 1Y2 VDD GND 2Y3 2Y2 S1

description
The CDCVF25084 is a high-performance, low-skew, low-jitter, phase-lock loop clock multiplier. It uses a PLL to precisely align, in both frequency and phase, the output clocks to the input clock signal including a multiplication factor of four. The CDCVF25084 operates from a nominal supply voltage of 3.3 V. The device also includes integrated series-damping resistors in the output drivers that make it ideal for driving point-to-point loads. Two banks of four outputs each provide low-skew, low-jitter copies of CLKIN x four. All outputs operate at the same frequency. Output duty cycles are adjusted to 50%, independent of duty cycle at CLKIN. The device automatically goes into power-down mode when no input signal is applied to CLKIN and the outputs go into a low state. Unlike many products containing PLLs, the CDCVF25084 does not require an external RC network. The loop filter for the PLL is included on-chip, minimizing component count, space, and cost. Because it is based on a PLL circuitry, the CDCVF25084 requ
ires a stabilization time to achieve phase lock of the feedback signal to the reference signal. This stabilization is required following power up and application of a fixed-frequency signal at CLKIN and any following changes to the PLL reference. The CDCVF25084 is characterized for operation from 40 C to 85 C.
FUNCTION TABLE S2 0 0 1 S1 0 1 0 1Y0 1Y3 Hi-Z Active Active 2Y0 2Y3 Hi-Z Hi-Z Active OUTPUT SOURCE N/A PLL Input clock (PLL bypass) PLL PLL SHUTDOWN Yes No Yes No

1 1 Active Active A CLK input frequency < 2 MHz switches the outputs to low level.

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Copyright 2003, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

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