CY74FCT162501CT| Datasheet

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1CY74FCT162H501 T

Data sheet acquired from Cypress Semiconductor Corporation. Data sheet modified to remove devices not offered.

CY74FCT16501T CY74FCT162501T CY74FCT162H501T

SCCS057B - August 1994 - Revised September 2001

18-Bit Registered Transceivers
Functional Description
These 18-bit universal bus transceivers can be operated in transparent, latched or clock modes by combining D-type latches and D-type flip-flops. Data flow in each direction is controlled by output enable (OEAB and OEBA), latch enable (LEAB and LEBA), and clock inputs (CLKAB and CLKBA). For A-to-B data flow, the device operates in transparent mode when LEAB is HIGH. When LEAB is LOW, the A data is latched if CLKAB is held at a HIGH or LOW logic level. If LEAB is LOW, the A bus data is stored in the latch/flip-flop on the LOW-to-HIGH transition of CLKAB. OEAB performs the output enable function on the B port. Data flow from B-to-A is similar to that of A-to-B and is controlled by OEBA, LEBA, and CLKBA. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The CY74FCT16501T is ideally suited for driving high-capacitance loads and low-impedance backplanes. THE CY74FC
T162501T has 24-mA balanced output drivers with current limiting resistors in the outputs. This reduces the need for external terminating resistors and provides for minimal undershoot and reduced ground bounce. The CY74FCT162501T is ideal for driving transmission lines. The CY74FCT162H501T is a 24-mA balanced output part, that has "bus hold" on the data inputs. The device retains the input's last state whenever the input goes to high impedance. This eliminates the need for pull-up/down resistors and prevents floating inputs.

Features
Ioff supports partial-power-down mode operation Edge-rate control circuitry for significantly improved noise characteristics Typical output skew < 250 ps ESD > 2000V TSSOP (19.6 mil pitch) and SSOP (25-mil pitch) packages Industrial temperature range of -40 C to +85 C VCC = 5V 10% CY74FCT16501T Features: 64 mA sink current, 32 mA source current Typical VOLP (ground bounce) <1.0V at VCC = 5V, TA = 25 C CY74FCT162501T Features: Balanced 24 mA output drivers Reduced system switching noise Typical VOLP (ground bounce) <0.6V at VCC = 5V, TA= 25 C CY74FCT162H501T Features: Bus hold retains last active state Eliminates the need for external pull-up or pull-down resistors

Functional Block Diagram

Pin Configuration
SSOP/TSSOP Top View
OEAB LEAB A1 GND A2 A3 VCC A4 A5 A6 GND A7 A8 A9 A 10 A 11 A 12 GND A 13 A 14 A 15 VCC A 16 A 17 GND A 18 OEBA LEBA 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 GND CLKAB B1 GND B2 B3 VCC B4 B5 B6 GND B7 B8 B9 B10 B11 B12 GND B13 B14 B15 VCC B16 B17 GND B18 CLKBA GND FCT16501-2

OEAB CLKBA LEBA OEBA CLKAB LEAB
C C D

C D

TO 17 OTHER CHANNELS

FCT16501-1

2001, Texas Instruments Incorporated