LVC2G86-1_8| Datasheet

LVC2G86-1_8, LVC2G86-2_5, LVC2G86-3_3, LVC2G86-5_0

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SN74LVC2G86 DUAL 2-INPUT EXCLUSIVE-OR GATE
www.ti.com
SCES360H AUGUST 2001 REVISED FEBRUARY 2007

FEATURES
Available in the Texas Instruments NanoFreeTM Package Supports 5-V VCC Operation Inputs Accept Voltages to 5.5 V Max tpd of 4.7 ns at 3.3 V Low Power Consumption, 10-uA Max ICC 24-mA Output Drive at 3.3 V Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25 C
DCT PACKAGE (TOP VIEW)

Typical VOHV (Output VOH Undershoot) >2 V at VCC = 3.3 V, TA = 25 C Ioff Supports Partial-Power-Down Mode Operation Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II ESD Protection Exceeds JESD 22 2000-V Human-Body Model (A114-A) 200-V Machine Model (A115-A) 1000-V Charged-Device Model (C101)
YZP PACKAGE (BOTTOM VIEW)

DCU PACKAGE (TOP VIEW)

1A 1B 2Y GND

1 2 3 4

8 7 6 5

VCC 1Y 2B 2A

1A 1B 2Y GND

1 2 3 4

8 7 6 5

VCC 1Y 2B 2A

GND 2Y 1B 1A

4 5 3 6 2 7 1 8

2A 2B 1Y VCC

See mechanical drawings for dimensions.

DESCRIPTION/ORDERING INFORMATION
This dual 2-input exclusive-OR gate is designed for 1.65-V to 5.5-V VCC operation. The SN74LVC2G86 performs the Boolean function Y = A B or Y = AB + AB in positive logic. NanoFreeTM package technology is a major breakthrough in IC packaging concepts, using the die as the package. A common application is as a true/complement element. If the input is low, the other input is reproduced in true form at the output. If the input is high, the signal on the other input is reproduced inverted at the output. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. ORDERING INFORMATION
TA PACKAGE (1) NanoFreeTM WCSP (DSBGA) 0.23-mm Large Bump YZP (Pb-free) 40 C to 85 C SSOP DCT VSSOP DCU (1) (2) Reel of 3000 Reel of 3000 Reel of 3000 Reel of 250 ORDERABLE PART NUMBER SN74LVC2G86YZPR SN74LVC2G86DCTR SN74LVC2G86DCUR SN74LVC2G86DCUT TOP-SIDE MARKING (2) _ _ _CH_ C86_ _ _ C86_

Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. DCT: The actual top-side marking has three additional characters that designate the year, month, and assembly/test site. DCU: The actual top-side marking has one additional character that designates the assembly/test site. YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, = Pb-free).

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. NanoFree is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.