SN74BCT29854| Datasheet

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SN74BCT29854 8 BIT TO 9 BIT PARITY BUS TRANSCEIVER
SCBS257 - SEPTEMBER 1987 - REVISED NOVEMBER 1993

BiCMOS Process With TTL Inputs and Outputs State-of-the-Art BiCMOS Design Significantly Reduces Standby Current Flow-Through Pinout (All Inputs on Opposite Side From Outputs) Functionally Equivalent to AMD Am29854 High-Speed Bus Transceiver With Parity Generator/ Checker Parity-Error Flag With Open-Collector Output Latch for Storage of the Parity-Error Flag Package Options Include Plastic Small-Outline (DW) Packages and Standard Plastic 300-mil DIPs (NT)

DW OR NT PACKAGE (TOP VIEW)

OEA A1 A2 A3 A4 A5 A6 A7 A8 ERR CLR GND

1 2 3 4 5 6 7 8 9 10 11 12

24 23 22 21 20 19 18 17 16 15 14 13

VCC B1 B2 B3 B4 B5 B6 B7 B8 PARITY OEB LE

description
The SN74BCT29854 is an 8-bit to 9-bit parity transceiver designed for asynchronous communication between data buses. When data is transmitted from the A to B bus, a parity bit is generated. When data is transmitted from the B to A bus with its corresponding parity bit, the parity-error (ERR) output will indicate whether or not an error in the B data has occurred. The output-enable (OEA, OEB) inputs can be used to disable the device so that the buses are effectively isolated. A 9-bit parity generator/ checker generates a parity-odd (PARITY) output and monitors the parity of the I/O ports with an open-collector parity-error (ERR) flag. ERR can be either passed, sampled, stored, or cleared from the latch using the latch-enable (LE) and clear (CLR) control inputs. When both OEA and OEB are low, data is transferred from the A bus to the B bus and inverted parity is generated. Inverted parity is a forced error condition which gives the designer more system diagnostic capability. The SN74BCT29854 provides inverting
logic. The SN74BCT29854 is characterized for operation from 0 C to 70 C.
FUNCTION TABLE INPUTS OEB L H H X OEA H L L X CLR X X H L H L X X X LE X L H H H H L L X Ai of H's Odd Even NA NA X X X L Odd H Even Odd Even Bi of L's NA Odd Even X X A NA B X X OUTPUT AND I/O B A NA NA NA PARITY H L NA NA NA ERR NA H L N-1 H NC H L H NA FUNCTION

A data to B bus and generate parity B data to A bus and check parity Store error flag Clear error-flag register Isolation

L H

A data to B bus and generate inverted parity

NA = not applicable, NC = no change, X = don't care Summation of low-level inputs includes PARITY along with Bi inputs. Output states shown assume the ERR output was previously high. In this mode, the ERR output, when enabled, shows noninverted parity of the A bus.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

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