SN74LVT18512| Datasheet

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SN54LVT18512, SN54LVT182512, SN74LVT18512, SN74LVT182512 3.3-V ABT SCAN TEST DEVICES WITH 18-BIT UNIVERSAL BUS TRANSCEIVERS
SCBS711 OCTOBER 1997

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Members of the Texas Instruments SCOPE TM Family of Testability Products Members of the Texas Instruments Widebus TM Family State-of-the-Art 3.3-V ABT Design Supports Mixed-Mode Signal Operation (5-V Input and Output Voltages With 3.3-V VCC) Support Unregulated Battery Operation Down to 2.7 V UBT TM (Universal Bus Transceiver) Combines D-Type Latches and D-Type Flip-Flops for Operation in Transparent, Latched, or Clocked Mode B-Port Outputs of 'LVT182512 Devices Have Equivalent 25- Series Resistors, So No External Resistors Are Required Compatible With the IEEE Std 1149.1-1990 (JTAG) Test Access Port and Boundary-Scan Architecture SCOPE TM Instruction Set IEEE Std 1149.1-1990 Required Instructions and Optional CLAMP and HIGHZ Parallel-Signature Analysis at Inputs Pseudo-Random Pattern Generation From Outputs Sample Inputs/Toggle Outputs Binary Count From Outputs Device Identification Even-Parity Opcodes Package Options Include 64-Pin Plastic Thin Shrink Small Outline (DGG) and 64-Pin Ceramic Du
al Flat (HKC) Packages Using 0.5-mm Center-to-Center Spacings

SN54LVT18512, SN54LVT182512 . . . HKC PACKAGE SN74LVT18512, SN74LVT182512 . . . DGG PACKAGE (TOP VIEW)

1CLKAB 1LEAB 1OEAB 1A1 1A2 GND 1A3 1A4 1A5 VCC 1A6 1A7 1A8 GND 1A9 2A1 2A2 2A3 GND 2A4 2A5 2A6 VCC 2A7 2A8 2A9 GND 2OEAB 2LEAB 2CLKAB TDO TMS

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33

1CLKBA 1LEBA 1OEBA 1B1 1B2 GND 1B3 1B4 1B5 VCC 1B6 1B7 1B8 GND 1B9 2B1 2B2 2B3 GND 2B4 2B5 2B6 VCC 2B7 2B8 2B9 GND 2OEBA 2LEBA 2CLKBA TDI TCK

description
The 'LVT18512 and 'LVT182512 scan test devices with 18-bit universal bus transceivers are members of the Texas Instruments SCOPE TM testability integrated-circuit family. This family of devices supports IEEE Std 1149.1-1990 boundary scan to facilitate testing of complex circuit-board assemblies. Scan access to the test circuitry is accomplished via the 4-wire test access port (TAP) interface. Additionally, these devices are designed specifically for low-voltage (3.3-V) VCC operation, but with the capability to provide a TTL interface to a 5-V system environment.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. SCOPE, Widebus, and UBT are trademarks of Texas Instruments Incorporated.
UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303

DALLAS, TEXAS 75265