sum110n0| Datasheet

Datasheet preview, take a look at Datasheets before downloading (Data Sheet is available on manufacturer site)

SPICE Device Model SUM110N04-2m1P Vishay Siliconix N-Channel 40-V (D-S) MOSFET
CHARACTERISTICS
N-Channel Vertical DMOS Macro Model (Subcircuit Model) Level 3 MOS Apply for both Linear and Switching Application Accurate over the - 55 C to 125 C Temperature Range Model the Gate Charge, Transient, and Diode Reverse Recovery Characteristics

DESCRIPTION
The attached spice model describes the typical electrical characteristics of the N-channel vertical DMOS. The subcircuit model is extracted and optimized over the - 55 C to 125 C temperature ranges under the pulsed 0 V to 10 V gate drive. The saturated output impedance is best fit at the gate bias near the threshold voltage. A novel gate-to-drain feedback capacitance network is used to model the gate charge characteristics while avoiding convergence difficulties of the switched Cgd model. All model parameter values are optimized to provide a best fit to the measured electrical data and are not intended as an exact physical interpretation of the device.

SUBCIRCUIT MODEL SCHEMATIC

This document is intended as a SPICE modeling guideline and does not constitute a commercial product data sheet. Designers should refer to the appropriate data sheet of the same number for guaranteed specification limits. Document Number: 64215 S-82053-Rev. A, 01-Sep-08 www.vishay.com 1