FL0069| Datasheet

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Easy Reference Chart
PA5/PWM1/TOUT1 PA4/PWM0/TOUT0 PA3/PWM3/OC3 PA2/PWM2/OC2 PA1/PWM1/OC1 PA0/PWM0/OC0 PA6/PWM2/ECI PA7/PWM3 Rx_CLK Tx_CLK Rx_DV Rx_ER Tx_ER Tx_EN MDIO RxD3 RxD2 RxD1 RxD0 TxD0 TxD1 TxD2 TxD3 MDC CRS COL 135 126 117 SDA SCL VDD VDD VDD VSS VSS VSS PHI WP

eZ80F91 MCU
11 SCL PHI PB7 PB3 V DD PC4 PC0 X IN VDD PD6 PD2 Vss 10 PA0 PA1 V DD PB5 PB0 PC5 PC1 PLL_V DD
LOOP FILT_OUT

256K Flash

32-Bit GPIO

8KB SRAM

EMAC

A0 A1 A2 A3 A4 VDD
VSS

108

VSS

PB7/MOSI PB6/MISO PB5/IC3 PB4/IC2 PB3/SCK PB2/SS PB1/IC1

144-Ball Grid Array
A1 ball pad corner

12 A B C D E F G H J K L M

12
A B C D E F G H J K L M

9 PA4 PA3 PA5 V ss PB4 V ss PC2 V DD PD4 TDI TCK
HALT_ SLPn

8 PA7 V DD V ss CRS PA2 PB2 PC6 PD7
TRIGOUT

7 COL TxD3 TxD2 TxD1 Tx_ER PA6 PLL_V ss TMS
RTC_ VDD

6 TxD0 Tx_EN Tx_CLK Rx_ER RxD0 A9 V ss V ss NMIn RESETn WAITn INSTRDn

5 V DD V ss Rx_CLK RxD2 A5 A17 A23 D5 WRn RDn MREQn IORQn

4 Rx_DV RxD1 RxD3 A4 A11 A15 A20 V ss D2 VDD D6 D7

3 MDC MDIO A3 A8 V ss A14 V ss A21 CS0n D1 D4 D3

2 WPn A2 V ss A6 V DD A13 V DD A19 VDD CS2n D0 Vss

1 A0 A1 V DD A7 A10 A12 A16 A18 A22 CS1n CS3n VDD

2 UART

I2C

A5 A6 A7 A8 A9

PB0/IC0/EC0 99 VSS VDD

O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O

SDA V ss PB6 PB1 PC7 PC3 V ss X OUT Vss PD5 PD1 PD0

PC7/RI1 PC6/DCD1 PC5/DSR1 PC4/DTR1 PC3/CTS1 18

A10

WDT

RTC

eZ80F91 MCU

SPI

VDD
VSS

A11

A12 A13 A14 A15

JTAG

A16 VDD A17 A18 A19
VSS

144-Pin Low-Profile Quad Flat Package

PC2/RTS1 PC1/RxD1 90 PC0/TxD1 VSS VDD XIN

PLL_VDD XOUT

PLL_VSS 27 VSS 81

LOOP_FILT VDD

PLL

4 PRT

A20 A21 A22 A23 Vss CS0 VDD

PD7/R10 PD6/DCD0 PD5/DSR0 PD4/DTR0 PD3/CTS0 PD2/RTS0 PD1/RxD0/IR_RxD 45 54 63 72 36 PD0/TxD0/IR_TxD

PD3 TRSTn TDO

Vss
RTC_ XOUT RTC_ XIN

VDD
BUSACKn BUSREQn

IRDA

4 Chip Selects

Internal RC OSC

ZDI

CS1 CS2 CS3

RESET

HALT_SLP

TRIGOUT

BUSREQ

BUSACK

INSTRD

RTC_VDD

TRST

WAIT

TCK

VDD

VSS

TDI

RTC_XIN

MREQ

NMI

RTC_XOUT

IORQ

TDO

TMS

VSS

Vss D0

Chip Select Registers
Chip Select x Lower Bound Register CS0_LBR = 00A8h, CS1_LBR = 00ABh, CS2_LBR = 00AEh, CS3_LBR = 00B1h

GPIO Registers
GPIO Mode Selection
GPIO Mode 1 2 3 4 5 6 7 8 9 Px_ALT2 Bits [7:0] 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Px_ALT1 Bits [7:0] 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 Px_DDR Bits [7:0] 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 Px_DR Bits [7:0] 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Port Mode Output Output Input from pin Input from pin Open-drain output Open-drain I/O Open-source I/O Open-source output Reserved Interrupt dual edge triggered Port B, C, or D alternative function controls port I/O Port B, C, or D alternative function controls port I/O Interrupt active Low Interrupt active High Interrupt falling edge triggered Interrupt rising edge triggered High impedance High impedance High impedance High impedance Output 0 1 High impedance High impedance 0 High impedance High impedance 1 High impedance High impedance

7:0

CSx_LBR

0 = Lower bound of the Memory Chip Select address range.* 1 = Address value of the I/O Chip Select.*

Chip Select x Upper Bound Register CS0_UBR = 00A9h, CS1_UBR = 00AC, CS2_UBR = 00AFh, CS3_UBR = 00B2h

Port x Alternate Registers 2 PA_ALT2 = 0099h, PB_ALT2 = 009Dh, PC_ALT2 = 00A1h, PD_ALT2 = 00A5h Port x Alternate Registers 1 PA_ALT1 = 0098h, PB_ALT1 = 009Ch, PC_ALT1 = 00A0h, PD_ALT1 = 00A4h Port x Alternate Registers 0 PA_ALT0 = 00A6h, PB_ALT0 = 00A7h, PC_ALT0 = 00CEh, PD_ALT0 = 00CFh Port x Data Direction Registers PA_DDR = 0097h, PB_DDR = 009Bh, PC_DDR = 009Fh, PD_DDR = 00A3h Port x Data Registers PA_DR = 0096h, PB_DR = 009Ah, PC_DR = 009Eh, PD_DR = 00A2h Px_ALT2 Px_ALT1 Px_ALT0 Px_DDR Px_DR

Power-Down Registers
Clock Peripheral Power-Down Register 1 CLK_PPD1 = 00DBh

Watch-Dog Timer Registers
Watch-Dog Timer Control Register WDT_CTL = 0093h

I2C Slave Address Register I2C_SAR = 00C8h

I2C Registers
7:1 0
SLA GCE 00h 7Fh: 7-bit slave address or upper 2 bits of address when operating in 10-bit mode. 0 = I2C not enabled to recognize the General Call Address. 1 = I2C enabled to recognize the General Call Address.

IrDA Registers
7:3 2 1 0
LOOP_BACK IR_RxEN IR_EN Reserved.

Infrared Encoder/Decoder Control Register IR_CTL = 00BFh

7 6 5 4 3 2 1 0

GPIO_D_OFF GPIO_C_OFF GPIO_B_OFF GPIO_A_OFF SPI_OFF I2C_OFF UART1_OFF UART0_OFF

0 = System clock to GPIO Port D is powered down.* 1 = System clock to GPIO Port D is powered up. 0 = System clock to GPIO Port C is powered down.* 1 = System clock to GPIO Port C is powered up. 0 = System clock to GPIO Port B is powered down.* 1 = System clock to GPIO Port B is powered up. 0 = System clock to GPIO Port A is powered down.* 1 = System clock to GPIO Port A is powered up. 0 = System clock to SPI is powered down. 1 = System clock to SPI is powered up. 0 = System clock to I2C is powered down. 1 = System clock to I2C is powered up. 0 = System clock to UART1 is powered down. 1 = System clock to UART1 is powered up. 0 = System clock to UART0 is powered down. 1 = System clock to UART0 is powered up.

7 6 5 4 3:2 1:0

WDT_EN NMI_OUT RST_FLAG NMI_FLAG

0 = WDT is disabled. 1 = WDT is enabled.* 0 = WDT time-out resets the eZ80 CPU. 1 = WDT time-out generates a NMI to the CPU. 0 = RESET caused by external full-chip reset or ZDI reset. 1 = RESET caused by WDT time-out.* 0 = NMI caused by external source. 1 = NMI caused by WDT time-out.* 00 = WDT clock source is system clock. 01 = WDT clock source is Real-Time Clock source*. 10 = WDT clock source is internal RC oscillator. 11 = Reserved. 00 = WDT time-out period is 227 clock cycles. 01 = WDT time-out period is 225 clock cycles. 10 = WDT time-out period is 222 clock cycles. 11 = WDT time-out period is 218 clock cycles.

0 = Internal LOOPBACK mode is disabled. 1 = Internal LOOPBACK mode is enabled.* 0 = IR_RXD data is ignored. 1 = IR_RXD data is passed to the UART0 RxD. 0 = Infrared Encoder/Decoder is disabled. 1 = Infrared Encoder/Decoder is enabled.

7:0

CSx_UBR

0 = Upper bound of the Memory Chip Select address range.* 1 = No effect.

7 6 5 4 3 2 1 0

Mode for Px7, where x = Port A, B, C, or D. Mode for Px6, where x = Port A, B, C, or D. Mode for Px5, where x = Port A, B, C, or D. Mode for Px4, where x = Port A, B, C, or D. Mode for Px3, where x = Port A, B, C, or D. Mode for Px2, where x = Port A, B, C, or D. Mode for Px1, where x = Port A, B, C, or D Mode for Px0, where x = Port A, B, C, or D.

I2C Extended Slave Address Register I2C_XSAR = 00C9h

Chip Select x Control Register CS0_CTL = 00AAh, CS1_CTL = 00ADh, CS2_CTL = 00B0h, CS3_CTL = 00B3h 000 = 0 wait states are asserted when this chip select is active. 001 = 1 wait state is asserted when this chip select is active. 010 = 2 wait states are asserted when this chip select is active. 011 = 3 wait states are asserted when this chip select is active. 100 = 4 wait states are asserted when this chip select is active. 101 = 5 wait states are asserted when this chip select is active. 110 = 6 wait states are asserted when this chip select is active. 111 = 7 wait states are asserted when this chip select is active. 0 = Chip Select is configured as a Memory Select. 1 = Chip Select is configured as an I/O Chip Select. 0 = Chip Select is disabled. 1 = Chip Select is enabled. Reserved.

WDT_CLK

7:0

SLAX

00h FFh: Least significant 8 bits of the 10-bit extended slave address.

I2C Data Register I2C_DR = 00CAh

WDT_PERIOD

7:5

CSx_WAIT

7:0

DATA

00h FFh: I2C data byte.

4 3 2:0

CSx_IO CSx_EN

Clock Peripheral Power-Down Register 2 CLK_PPD2 = 00DCh

Watch-Dog Timer Reset Register WDT_RR = 0094h

I2C Control Register I2C_CTL = 00CBh

Multi-PWM Control Registers
0 = I C interrupt is disabled. 1 = I2C interrupt is enabled. 0 = The I2C bus is disabled and all inputs are ignored. 1 = The I2C bus is enabled.* 0 = A master mode START condition is sent. 1 = A master mode start-transmit condition on the bus. 0 = A master mode STOP condition is sent. 1 = A master mode stop-transmit condition on the bus. 0 = The I2C interrupt flag is not set. 1 = The I2C interrupt flag is set. 0 = Not Acknowledge. 1 = Acknowledge. Reserved.
2

7 6

PHI_OFF VBO_OFF

0 = PHI clock output is enabled. 1 = PHI clock output is disabled.* 0=VBO detection circuit is enabled 1=VBO detection circuit is disabled Reserved.

7:0

WDT_RR

A5h = The first Write value required to reset the WDT prior to a time-out. 5Ah = The second Write value required to reset the WDT prior to a time-out.*

7 6 5 4

IEN ENAB STA STP IFLG AAK

PWM Control Register 1 PWM_CTL1 = 0079h

7 6 5 4 3 2 1 0

PAIR_EN PT_EN MM_EN PWM3_EN PWM2_EN PWN1_EN PWM0_EN MPWM_EN

0 = Global disable of the PWM outputs.* 1 = Global enable of the PWM and PWM output pairs. 0 = Disable power-trip feature. 1 = Enable power-trip feature. 0 = Disable Master mode. 1 = Enable Master mode. 0 = Disable PWM generator 3. 1 = Enable PWM generator 3. 0 = Disable PWM generator 2. 1 = Enable PWM generator 2. 0 = Disable PWM generator 1. 1 = Enable PWM generator 1. 0 = Disable PWM generator 0. 1 = Enable PWM generator 0. 0 = Disable Multi-PWM mode. 1 = Enable Multi-PWM mode.

Chip Select x Bus Mode Control Register CS0_BMC = 00F0h, CS1_BMC = 00F1h, CS2_BMC = 00F2h, CS3_BMC = 00F3h

EMAC Registers
EMAC Test Register EMAC_TEST = 0020h

5:4
EMAC PHY Unit Select Address Register EMAC_FIAD = 003Fh

3 2 1 0

TIMER2_OFF TIMER1_OFF TIMER0_OFF TIMER0_OFF

0 = System clock to TIMER2 is powered down. 1 = System clock to TIMER2 is powered up. 0 = System clock to TIMER1 is powered down. 1 = System clock to TIMER1 is powered up. 0 = System clock to TIMER0 is powered down. 1 = System clock to TIMER0 is powered up. 0 = System clock to TIMER0 is powered down. 1 = System clock to TIMER0 is powered up.

7:6 5 4

BUS_MODE

00 = eZ80 bus mode. 01 = Z80 bus mode. 10 = Intel bus mode. 11 = Motorola bus mode. 0 = Separate address and data. 1 = Multiplexed address and data on DATA[7:0]. Reserved. 0000 = Not valid. 0001 = Each bus mode state is 1 eZ80 clock cycle in duration.* 0010 = Each bus mode state is 2 eZ80 clock cycles in duration. 0011 = Each bus mode state is 3 eZ80 clock cycles in duration. 0100 = Each bus mode state is 4 eZ80 clock cycles in duration. 0101 = Each bus mode state is 5 eZ80 clock cycles in duration. 0110 = Each bus mode state is 6 eZ80 clock cycles in duration. 0111 = Each bus mode state is 7 eZ80 clock cycles in duration. 1000 = Each bus mode state is 8 eZ80 clock cycles in duration. 1001 = Each bus mode state is 9 eZ80 clock cycles in duration. 1010 = Each bus mode state is 10 eZ80 clock cycles in duration. 1011 = Each bus mode state is 11 eZ80 clock cycles in duration. 1100 = Each bus mode state is 12 eZ80 clock cycles in duration. 1101 = Each bus mode state is 13 eZ80 clock cycles in duration. 1110 = Ea
ch bus mode state is 14 eZ80 clock cycles in duration. 1111 = Each bus mode state is 15 eZ80 clock cycles in duration.

PLL Registers
PLL Divider Register Low Bytes PLL_DIV_L = 005Ch

3 2 1:0

7 6 5 4 3 2 1 0
TEST_FIFO TxRx_SEL SSTC SIMR FRC_OVR_ERR FRC_UND_ERR LPBK

Reserved. 0 = FIFO test mode disabled normal operation. 1 = FIFO test mode enabled. 0 = Select the Receive FIFO when FIFO test mode is enabled. 1 = Select the Transmit FIFO when FIFO test mode is enabled. 0 = Normal operation. 1 = Shortcut slot timer counter.* 0 = Normal operation. 1 = Simulation Reset. 0 = Normal operation. 1 = Force overrun error in Receive FIFO. 0 = Normal operation. 1 = Force underrun error in Transmit FIFO. 0 = Normal operation. 1 = EMAC Transmit interface is looped back into EMAC Receive Interface.

7:5 4:0
FIAD

Reserved. 00h 1Fh: 5-bit address of external PHY unit.

AD_MUX

7:0

PLL_DIV_L

00h FFh: These bits represent the Low byte of the 11-bit PLL divider value.*

EMAC Transmit Polling Timer Register EMAC_PTMR = 0040h

PLL Divider Register High Byte PLL_DIV_H = 005Dh

I2C Status Register I2C_SR = 00CCh

7:0

EMAC_PTMR

00h FFh: The Transmit polling period in units of SYSCLK 256. 00 = Disables Transmit polling timer.

7:3

Reserved. PLL_DIV_H 0h 7h: These bits represent the High byte of the 11-bit PLL divider value.*

7:3 2:0

STAT

00000 11111: 5-bit I2C status code. Reserved.

EMAC Reset Control Register EMAC_RST = 0041h

UART Control Registers
UART Baud Rate Generator Registers Low Byte UART0_BRG_L = 00C0h, UART1_BRG_L = 00D0h

2:0

PWM Control Register 2 PWM_CTL2 = 007Ah

3:0

BUS_CYCLE

7:6 5 4 3 2 1 0
SRST HRTFN HRRFN HRTMC HRRMC HRMGT

Reserved. 1 = Software reset active.* 0 = Normal operation. 1 = Reset transmit function. 0 = Normal operation. 1 = Reset receive function. 0 = Normal operation. 1 = Reset EMAC transmit control function. 0 = Normal operation. 1 = Reset EMAC receive control function. 0 = Normal operation. 1 = Reset EMAC management function. 0 = Normal operation.

PLL Control Register 0 PLL_CTL0 = 005Eh

I2C Clock Control Register I2C_CCR = 00CCh 00 = Charge pump current = 100 uA. 01 = Charge pump current = 500 uA. 10 = Charge pump current = 1.0 mA. 11 = Charge pump current = 1.5 mA. Reserved.

7:6 5:4

AON_EN

00 = Disable AND/OR features on PWM. 01 = Enable AND logic on PWM. 10 = Enable OR logic on PWM. 11 = Disable AND/OR features on PWM. 00 = Disable AND/OR features on PWM. 01 = Enable AND logic on PWM. 10 = Enable OR logic on PWM. 11 = Disable AND/OR features on PWM. Amount of delay between falling edge of PWM (PWM) and rising edge of PWM (PWM). 0000 = None 1000 = 8 SCLK periods 0001 = 1 SCLK period 1001 = 9 SCLK periods 0010 = 2 SCLK periods 1010 = 10 SCLK periods 0011 = 3 SCLK periods 1011 = 11 SCLK periods 0100 = 4 SCLK periods 1100 = 12 SCLK periods 0101 = 5 SCLK periods 1101 = 13 SCLK periods 0110 = 6 SCLK periods 1110 = 14 SCLK periods 0111 = 7 SCLK periods 1111 = 15 SCLK periods

7:0

UARTx_BRG_L

00h FFh: These bits represent the Low byte of the 16-bit Baud Rate Generator divider value.*

7:6 5:4 3:2 1:0

CHRP_CTL1

7 6:3 2:0
M N

Reserved. 0000 1111: I2C clock divider scalar value. 000 111: I2C clock divider exponent.

AO_EN

EMAC Configuration Register 1 EMAC_CFG1 = 0021h

7 6 5 4 3 2 1 0

PADEN ADPADN VLPAD CRCEN FULLD FLCHK HUGEN DCRCC

0 = No padding.* 1 = EMAC pads all short frames at the end of the data field. 0 = Disable auto detection. 1 = Enable frame detection.* 0 = Do not pad all short frames. 1 = EMAC pads all short frames to 64 bytes and append a valid CRC. 0 = Do not append CRC. 1 = Append CRC to every frame regardless of padding options. 0 = Half-duplex mode, CSMA/CD enabled.* 1 = Enable full duplex mode, CSMA/CD disabled.* 0 = Ignore the length field within Transmit/Receive frames. 1 = Transmit Receive frame lengths compared to the length/type field.* 0 = Limit the Receive frame size to the number of bytes specified.* 1 = Allow unlimited-sized frames to be received. 0 = No proprietary header.* 1 = Proprietary header exists on the front of IEEE 802.3 frames.

UART Baud Rate Generator Registers High Byte UART0_BRG_H = 00C1h, UART1_BRG_H = 00D1h

7:0

UARTx_BRG_H

00h FFh: These bits represent the High byte of the16-bit Baud Rate Generator divider value.*

LDS_CTL1

UART Transmit Holding Registers UART0_THR = 00C0h, UART1_THR = 00D0h

CLK_MUX

Real-Time Clock Registers
Real-Time Clock Seconds Register RTC_SEC = 00E0h Binary-Coded-Decimal Operation (BCD_EN = 1)

EMAC Transmit Lower Boundary Pointer Registers Low and High Bytes EMAC_TLBP_L = 0042h, EMAC_TLBP_H = 0043h*

7:0

TxD

Transmit data byte. PLL Control Register 1 PLL_CTL = 005Fh

00 = Lock criteria 8 consecutive cycles of 20ns. 01 = Lock criteria 16 consecutive cycles of 20ns. 10 = Lock criteria 8 consecutive cycles of 400ns. 11 = Lock criteria 16 consecutive cycles of 400ns. 00 = System clock source is the external crystal oscillator. 01 = System clock source is the PLL.* 10 = System clock source if the Real-Time Clock crystal oscillator. 11 = Reserved.*

I2C Software Reset Register I2C_SRR = 00CDh

3:0

PWM_DLY

7:0

SRR

00h FFh: Writing any value to this register performs a software 2 reset of the I2C module.

7:0

EMAC_TLBP_x

0000h FFFFh: EMAC_TLBP_H = TLBP [15:8] EMAC_TLBP_L = TLBP [7:0]

UART Receive Buffer Registers UART0_RBR = 00C0h, UART1_RBR = 00D0h

PWM Control Register 3 PWM_CTL3 = 007Bh Reserved.

7:6 5 4 3 2 1 0
LCK_STATUS INT_LOCK INT_UNLOCK INT_LOCK_EN INT_UNLOCK_EN PLL_ENABLE

7:4 3:0 7:0

TEN_SEC SEC

0 5 = The tens digit of the current seconds count. 0 9 = The ones digit of the current seconds count.

EMAC Boundary Pointer Registers Low, High, and Upper Bytes EMAC_BP_L = 0044h, EMAC_BP_H = 0045h, EMAC_BP_U = 0046h

7:0

RxD

Receive data byte.

0 = PLL is currently out of lock. 1 = PLL is currently locked. 0 = Lock signal from PLL has not risen since last read.* 1 = Interrupt generated when PLL enters lock mode.* 0 = Lock signal from PLL has not fallen since last read.* 1 = Interrupt generated when PLL goes out of lock mode.* 0 = Interrupt generation for PLL locked condition is disabled.* 1 = Interrupt generation for PLL locked condition is enabled.* 0 = Interrupt generation for PLL unlocked condition is disabled.* 1 = Interrupt generation for PLL unlocked condition is enabled.* 0 = PLL is disabled.* 1 = PLL is enabled.

Timer Registers
Timer Control Register TMR0_CTL = 0060h, TMR1_CTL = 0065h, TMR2_CTL = 006Fh, TMR3_CTL = 0074h

7:4 3 2 1 0

PT_ICx_EN X[3:0] PT_TRI PT_LVL PT_LVL_N PTD

0 = Power trip disabled on ICx. 1 = Power trip enabled on ICx. 0 = All PWM trip levels are tristate. 1 = All PWM trip levels are defined by PT_LVL and PT_LVL_N. 0 = After power trip, PWMx outputs are set to one. 1 = After power trip, PWMx outputs are set to zero. 0 = After power trip, PWMx outputs are set to one. 1 = After power trip, PWMx outputs are set to zero. 0 = Power trip has been cleared. 1 = This bit is set after power trip event.

Binary Operation (BCD_EN = 0) SEC 00h 3Bh = The current seconds count.

EMAC Configuration Register 2 EMAC_CFG2 = 0022h

7:0

EMAC_BP_x

0000h FFFFh: EMAC_BP_U = BP [23:16] EMAC_BP_H = BP [15:8] EMAC_BP_L = BP [7:0]

UART Interrupt Enable Registers UART0_IER = 00C1h, UART1_IER = 00D1h

7:5 4 3 2 1 0
TCIE MIIE LSIE TIE RIE

Reserved. 0 = Transmission complete interrupt is disabled. 1 = Transmission complete interrupt is generated.* 0 = Modem interrupt on edge detect of status inputs disabled. 1 = Modem interrupt on edge detect of status inputs enabled. 0 = Line status interrupt is disabled. 1 = Line status interrupt is enabled.* 0 = Transmit interrupt is disabled. 1 = Transmit interrupt is enabled.* 0 = Receive interrupt is disabled. 1 = Receive interrupt is enabled.*

7 6:5 4:3 2

BRK_STOP

0 = Timer continues operating during debug break points. 1 = Timer stops operating and holds count value at breakpoint. 00 = Timer source is the system clock divided by the prescaler. 01 = Timer source is the Real Time Clock Input. 10 = Timer source is the Event Count (ECx) input falling edge.* 11 = Timer source is the Event Count (ECx) input rising edge.* 00 = System clock divider = 4. 01 = System clock divider = 16. 10 = System clock divider = 64. 11 = System clock divider = 256. 0 = Timer operates in SINGLE PASS mode.* 1 = Timer operates in CONTINUOUS mode.* 0 = Reload function is not forced. 1 = Force reload.* 0 = Programmable reload timer is disabled. 1 = Programmable reload timer is enabled.

7 6 5:0

BPNB NOBO LCOL

0 = Use normal back-off algorithm prior to transmitting packet.* 1 = EMAC immediately retransmits the packet without back-off.* 0 = Enable exponential back-off. 1 = EMAC immediately retransmits following a collision.* 00h 3Fh: Sets the number of bytes after Start Frame Delimiter.*

EMAC Receive High Boundary Pointer Registers Low and High Bytes EMAC_RHBP_L = 0047h, EMAC_RHBP_H = 0048h

CLK_SEL

Real-Time Clock Minutes Register RTC_MIN = 00E1h Binary-Coded-Decimal Operation (BCD_EN = 1)

7:0

EMAC_RHBP_x

00h FFh: These bits represent the Low/High byte of the 2-byte EMAC Receive High Boundary Pointer value {EMAC_RHBP_H, EMAC_BRHP_L}.*

CLK_DIV

7:4 3:0 7:0

TEN_MIN MIN

0 5 = The tens digit of the current minutes count. 0 9 = The ones digit of the current minutes count.

EMAC Configuration Register 3 EMAC_CFG3 = 0023h

EMAC Receive Read Pointer Registers Low and High Bytes EMAC_RRP_L = 0049h, EMAC_RRP_H = 004Ah

TIM_CONT RLD TIM_EN

Binary Operation (BCD_EN = 0) MIN 00h 3Bh = The current minutes count.

7 6 5 4 3:0

LONGP PUREP XSDFR BITMD RETRY

0 = Any preamble length allowed.* 1 = Only Receive packets with preamble fields of 12 bytes or less allowed. 0 = No preamble error checking performed. 1 = EMAC verifies the content of the preamble.* 0 = EMAC aborts when excessive deferral limit is reached. 1 = EMAC defers to the carrier indefinitely.* 0 = Disable 10 Mbps ENDEC mode. 1 = Enable 10 Mbps ENDEC mode. 0h Fh: Number of retransmission attempts following a collision.*

7:0

EMAC_RRP_x

0000h FFFFh: EMAC_RRP_H = RRP [15:8] EMAC_?RRP_L = RRP [7:0]

EMAC Buffer Size Register EMAC_BUFSZ = 004Bh

UART Interrupt Identification Registers UART0_IIR = 00C2h, UART1_IIR = 00D2h 00 = Set EMAC Rx/Tx buffer size to 256 bytes. 01 = Set EMAC Rx/Tx buffer size to 128 bytes. 10 = Set EMAC Rx/Tx buffer size to 64 bytes. 11 = Set EMAC Rx/Tx buffer size to 32 bytes. 00 = Disable Transmit Pause Control Frame generation.* 01 = Transmit Pause Control Frame level.*

Flash Control Registers
Flash Key Register FLASH_KEY = 00F5h

1 0

ZDI Registers
ZDI Address Match Registers ZDI_ADDR0_L = 00h, ZDI_ADDR0_H = 01h, ZDI_ADDR0_U = 02H, ZDI_ADDR1_L = 04h, ZDI_ADDR1_H = 05h, ZDI_ADDR1_U = 06H, ZDI_ADDR2_L = 08h, ZDI_ADDR2_H = 09h, ZDI_ADDR2_U = 0AH, ZDI_ADDR3_L = 0Ch, ZDI_ADDR3_H = 0Dh, ZDI_ADDR3_U = 0EH*

Real-Time Clock Hours Register RTC_HRS = 00E2h Binary-Coded-Decimal Operation (BCD_EN = 1)

7:6 5:0

BUFSZ

7:6 5:4 3:1 0

FSTS

00 = FIFO is disabled. 10 = Receive FIFO is disabled. 1 = FIFO is enabled. Reserved. 000 110: The Interrupt Status Code indicated in these three bits is valid only if INTBIT is 1.* 0 = An active interrupt source exists within the UART. 1 = No active interrupt source exists within the UART.

7:0

FLASH_KEY

B6h,49h: Sequential Write with the values B6h, 49h to this register will unlock the Flash.

Timer Interrupt Enable Register TMR0_IER = 0061h, TMR1_IER = 0066h, TMR2_IER = 0070h, TMR3_IER = 0075h

Flash Data Register FLASH_DATA = 00F6h

TPCF_LEV

INSTS INTBIT

7
00h FFh: Data value to write to Flash memory, or the data value that is read from Flash memory.

Unused. IRQ_OC3_EN IRQ_OC2_EN IRQ_OC1_EN IRQ_OC0_EN IRQ_ICB_EN IRQ_ICA_EN IRQ_EOC_EN 0 = Interrupt requests for OC3 are disabled.* 1 = Interrupt requests for OC3 are enabled.* 0 = Interrupt requests for OC2 are disabled.* 1 = Interrupt requests for OC2 are enabled.* 0 = Interrupt requests for OC1 are disabled.* 1 = Interrupt requests for OC1 are enabled.* 0 = Interrupt requests for OC0 are disabled.* 1 = Interrupt requests for OC0 are enabled.* 0 = Interrupt requests for IC1 or IC3 are disabled.* 1 = Interrupt requests for IC1 or IC3 are enabled.* 0 = Interrupt requests for IC0 or IC2 or PWM power trip are disabled.* 1 = Interrupt requests for IC0 or IC2 or PWM power trip are enabled.* 0 = Interrupt on end-of-count is disabled. 1 = Interrupt on end-of-count enabled.

7:0

ZDI_ADDRX_L, ZDI_ADDRX_H, or ZDI_ADDRX_U

000000h FFFFFFh: ZDI_ADDRX_U = ADDRX [23:16] ZDI_ADDRX_H = ADDRX [15:8] ZDI_ADDRX_L = ADDRX [7:0]

7:4 3:0 7:0

TEN_HRS HRS

0 2 = The tens digit of the current hours count. 0 9 = The ones digit of the current hours count.

7:0

FLASH_DATA

6 5 4 3 2 1 0

ZDI Break Control Register ZDI_BRK_CTL = 10h*

Binary Operation (BCD_EN = 0) HRS 00h 17h = The current hours count.

EMAC Configuration Register 4 EMAC_CFG4= 0024h

EMAC Interrupt Enable Register EMAC_IEN = 004Ch

7 6 5 4 3 2 1 0
TPCF THDF PARF RxFC TxFC TPAUSE RxEN

7 6 5 4 3 2 1 0

TxFSMERR MGTDONE Rx_CF Rx_PCF Rx_DONE Rx_OVR Tx_CF Tx_DONE

1 = Enable Transmit State Machine error interrupt.* 0 = Disable Transmit State Machine error interrupt.* 1 = Enable MII Management Done interrupt.* 0 = Disable MII M anagement Done interrupt.* 1 = Enable Receive Control Frame interrupt.* 0 = Disable Receive Control Frame interrupt.* 1 = Enable Receive Pause Control Frame interrupt.* 0 = Disable Receive Pause Control Frame interrupt.* 1 = Enable Receive Done interrupt.* 0 = Disable Receive Done interrupt.* 1 = Enable Receive Overrun interrupt.* 0 = Disable Receive Overrun interrupt.* 1 = Enable Transmit Control Frame interrupt.* 0 = Disable Transmit Control Frame interrupt.* 1 = Enable Transmit Done interrupt.* 0 = Disable Transmit Done interrupt.*

UART FIFO Control Registers UART0_FCTL = 00C2h, UART1_FCTL = 00D2h

Flash Address Upper Byte Register FLASH_ADDR_U = 00F7h

7 6 5 4 3 2 1 0

BRK_NEXT BRK_ADDR3 BRK_ADDR2 BRK_ADDR1 BRK_ADDR0 IGN_LOW_1 IGN_LOW_0 SINGLE_STEP

0 = ZDI break on the next CPU instruction is disabled.* 1 = ZDI break on the next CPU instruction is enabled.* 0 = ZDI break, upon matching break address 3, is disabled. 1 = ZDI break, upon matching break address 3, is enabled. 0 = ZDI break, upon matching break address 2, is disabled. 1 = ZDI break, upon matching break address 2, is enabled. 0 = ZDI break, upon matching break address 1, is disabled. 1 = ZDI break, upon matching break address 1, is enabled. 0 = ZDI break, upon matching break address 0, is disabled. 1 = ZDI break, upon matching break address 0, is enabled. 0 = Break on entire ADDR1. 1 = Break on upper 16 bits or ADDR1. 0 = Break on entire ADDR0. 1 = Break on upper 16 bits or ADDR0. 0 = ZDI SINGLE STEP mode is disabled. 1 = ZDI SINGLE STEP mode is enabled.*

Reserved. 0 = Do not transmit a pause control frame. 1 = Transmit pause control frame.* 0 = Disable back pressure. 1 = EMAC asserts back pressure on the link.* 0 = Only accept frames that meet preset criteria.* 1 = All frames are received.* 0 = EMAC ignores received pause control frames. 1 = EMAC acts upon pause control frames received. 0 = Pause control frames are not allowed to be transmitted. 1 = Pause control frames are allowed to be transmitted. 0 = Do not force a pause condition. 1 = Force a pause condition while this bit is asserted. 0 = Do not receive frames. 1 = Allow Receive frames to be received.

7:6 5:3 2 1 0

TRIG

Real-Time Clock Day-of-the-Week Register RTC_DOW = 00E3h Binary-Coded-Decimal Operation (BCD_EN = 1)

00 = Receive FIFO trigger level is set to 1.* 01 = Receive FIFO trigger level is set to 4.* 10 = Receive FIFO trigger level is set to 8.* 11 = Receive FIFO trigger level is set to 14.* Reserved must be 000b.

7:2 1:0

FLASH_ADDR_U

00h FCh: These bits define the upper byte of the Flash address.* Reserved.*

Flash Control Register FLASH_CTRL = 00F8h 000 = 0 001 = 1 010 = 2 011 = 3 100 = 4 101 = 5 110 = 6 111 = 7 wait states are inserted when Flash is active. wait states are inserted when Flash is active. wait states are inserted when Flash is active. wait states are inserted when Flash is active. wait states are inserted when Flash is active. wait states are inserted when Flash is active. wait states are inserted when Flash is active. wait states are inserted when Flash is active.

7:4 3:0 7:4 3:0
DOW DOW

Reserved. 1 7 = The current day-of-the-week count.

CLRTxF CLRRxF FIFOEN

0 = Transmit disable. 1 = Transmit enable. 0 = Receive disable. 1 = Receive enable. 0 = Transmit and receive FIFOs are disabled.* 1 = Transmit and receive FIFOs are enabled.

7:5

FLASH_WAIT

Binary Operation (BCD_EN = 0) Reserved. 01h 07h = The current day-of-the-week count.

Timer Interrupt Identification Register TMR0_IIR = 0062h, TMR1_IIR = 0067h, TMR2_IIR = 0071h, TMR3_IIR = 0076h

UART Line Control Registers UART0_LCTL = 00C3h, UART1_LCTL = 00D3h

4 3 2:0
FLASH_EN

Reserved. 0 = Flash memory access is disabled. 1 = Flash memory access is enabled. Reserved.

7 6 5 4 3 2 1 0
OC3 OC2 OC1 OC0 ICB ICA EOC

Unused. 0 = Output compare, OC3, does not occur. 1 = Output compare, OC3, occurs. 0 = Output compare, OC2, does not occur. 1 = Output compare, OC2, occurs. 0 = Output compare, OC1, does not occur. 1 = Output compare, OC1, occurs. 0 = Output compare, OC0, does not occur. 1 = Output compare, OC0, occurs. 0 = Input capture, ICB for IC1 or IC3, does not occur.* 1 = Input capture, ICB for IC1 or IC3, occurs.* 0 = Input capture, IC0 for IC3, or PWM power trip, does not occur.* 1 = Input capture, IC0 for IC3, or PWM power trip, occurs.* 0 = End-of-count does not occur. 1 = End-of-count occurs.

Real-Time Clock Day-of-the-Month Register RTC_DOM = 00E4h Binary-Coded-Decimal Operation (BCD_EN = 1)

EMAC Station Address Registers EMAC_STAD_0 = 0025h, EMAC_STAD_1 = 0026h, EMAC_STAD_2 = 0027h, EMAC_STAD_3 = 0028h, EMAC_STAD_4 = 0029h, EMAC_STAD_5 = 002Ah 00h FFh: This 48-bit station address comprises { EMAC_STAD_5 [7:0] = STAD [47:40], EMAC_STAD_4 [7.0] = STAD [39:32], EMAC_STAD_3 [7:0] = STAD [31:24], EMAC_STAD_2 [7:0] = STAD [23:16], EMAC_STAD_1 [7:0] = STAD [15:8], EMAC_STAD_0 [7:0] = STAD [7:0]}

EMAC Interrupt Status Register EMAC_ISTAT = 004Dh

7 6 5 4 3 2:0

DLAB SB FPE EPS PEN CHAR

0 = Access to UARTs is enabled.* 1 = Access to Baud Rate Generators is enabled.* 0 = Do not send a BREAK signal. 1 = Send a BREAK signal.* 0 = Do not force a parity error. 1 = Force a parity error.* 0 = Use odd parity for transmission.* 1 = Use even parity for transmission.* 0 = Parity bit transmit and receive is disabled. 1 = Parity bit transmit and receive is enabled.* 000 111: UART character parameter selection.*

ZDI Master Control Register ZDI_MASTER_CTL = 11h

7 6:0

ZDI_RESET

0 = No action. 1 = Initiate a RESET of the eZ80F91.* Reserved.

7 6 5 4 3 2 1 0

TxFSMERR_STAT MGTDONE_STAT Rx_CF_STAT Rx_PCF_STAT Rx_DONE_STAT Rx_OVR_STAT Tx_CF_STAT Tx_DONE_STAT

1 = Internal error occurred in the EMAC Transmit path.* 0 = Normal operation.* 1 = MII Mgmt. interrupt has completed a Read or Write access to PHY.* 0 = MII Mgmt. did not occur. 1 = Receive Control Frame interrupt occurred.* 0 = Receive Control Frame interrupt did not occur. 1 = Receive Pause Control Frame interrupt occurred.* 0 = Receive Pause Control Frame interrupt did not occur.* 1 = Receive Done interrupt occurred.* 0 = Receive Done interrupt did not occur.* 1 = Receive Overrun interrupt occurred.* 0 = Receive Overrun interrupt did not occur.* 1 = Transmit Control Frame interrupt occurred.* 0 = Transmit Control Frame interrupt did not occur.* 1 = Transmit Done interrupt occurred.* 0 = Transmit Done interrupt did not occur.*

7:4 3:0 7:0

Flash Frequency Divider Register FLASH_FDIV = 00F9h

TENS_DOM DOM

0 3 = The tens digit of the current day-of-the-month count. 0 9 = The ones digit of the current day-of-the-month count.

7:0

EMAC_STAD_x

7:0

FLASH_FDIV

01h FFh: Divider value for generating the required 5.1 6.5us Flash controller clock period.

ZDI Write Data Registers ZDI_WR_U = 13h, ZDI_WR_H = 14h, ZDI_WR_L= 15h*

Binary Operation (BCD_EN = 0) DOM 01h 1Fh = The current day-of-the-month count.

Flash Write/Erase Protection Register FLASH_PROT = 00FAh

7:0

ZDI_WR_L, ZDI_WR_H, or ZDI_WR_U

000000h FFFFFFh: Write operation defined by the ZDI_RW_CTRL register. {ZDI_WR_U = WDATA [23:16], ZDI_WR_H = WDATA[15:8], ZDI_WR_L = WDATA[7:0]}*

Real-Time Clock Month Register RTC_MON = 00E5h Binary-Coded-Decimal Operation (BCD_EN = 1)

EMAC Transmit Pause Timer Value Registers Low and High Bytes EMAC_TPTV_L = 002Bh, EMAC_TPTV_H = 002Ch

UART Modem Control Registers UART0_MCTL = 00C4h, UART1_MCTL = 00D4h

7 6 5 4 3 2 1 0

BLK7_PROT BLK6_PROT BLK5_PROT BLK4_PROT BLK3_PROT BLK2_PROT BLK1_PROT BLK0_PROT

0 = Disable Write/Erase Protect on block 38000h to 3FFFFh. 1 = Enable Write/Erase Protect on block 38000h to 3FFFFh. 0 = Disable Write/Erase Protect on block 30000h to 37FFFh. 1 = Enable Write/Erase Protect on block 30000h to 37FFFh. 0 = Disable Write/Erase Protect on block 28000h to 2FFFFh. 1 = Enable Write/Erase Protect on block 28000h to 2FFFFh. 0 = Disable Write/Erase Protect on block 20000h to 27FFFh. 1 = Enable Write/Erase Protect on block 20000h to 27FFFh. 0 = Disable Write/Erase Protect on block 18000h to 1FFFFh. 1 = Enable Write/Erase Protect on block 18000h to 1FFFFh. 0 = Disable Write/Erase Protect on block 10000h to 17FFFh. 1 = Enable Write/Erase Protect on block 10000h to 17FFFh. 0 = Disable Write/Erase Protect on block 08000h to 0FFFFh. 1 = Enable Write/Erase Protect on block 08000h to 0FFFFh. 0 = Disable Write/Erase Protect on block 00000h to 07FFFh. 1 = Enable Write/Erase Protect on block 00000h to 07FFFh.

7:0

EMAC_TPTV_x

00h FFh: The 16-bit value, {EMAC_TPTV_H, EMAC_TPTV_L}, is inserted into outgoing pause control frames.*

7 6 5 4 3 2 1 0
POLARITY MDM LOOP OUT2 OUT1 RTS DTR

Reserved. 0 = TxD and RxD signals normal polarity. 1 = Invert polarity of TxD and RxD signals. 0 = Multidrop mode disabled. 1 = Multidrop mode enabled.* 0 = LOOP BACK mode is disabled. 1 = LOOP BACK mode is enabled.* 0 1: No function in normal operation.* 0 1: No function in normal operation.* 0 1: Request to send.* 0 1: Data terminal ready.*

Timer Data Registers Low and High Bytes TMR0_DR_L = 0063h, TMR1_DR_L = 0068h, TMR2_DR_L = 0072h, TMR3_DR_L = 0077h,TMR0_DR_H = 0064h, TMR1_DR_H= 0069h, TMR2_DR_H = 0073h, TMR3_DR_H = 0078h

ZDI Read/Write Control Register ZDI_RW_CTL = 16h* 00 01 02 03 04 05 06 07 08 09 0A 0B Read {MBASE, A, F} Read BC Read DE Read HL Read IX Read IY Read SP Read PC Set ADL Reset ADL Exchange CPU register sets Read memory from current PC value, increment PC 80 81 82 83 84 85 86 87 88 89 8A 8B Write AF ? Write BC Write DE Write HL Write IX Write IY Write SP Write PC Reserved Reserved Reserved Write memory from current PC value, increment PC

7:4 3:0 7:0

TENS_MON MON

0 1 = The tens digit of the current month count. 0 9 = The ones digit of the current month count.

EMAC Interpacket Gap Register EMAC_IPGT = 002Dh

Note: Write a 1 to clear bit.

7:0

TMR_DR_x

00h FFh: TMRx_DR_H = TDATA [15:8] TMRx_DR_L = TDATA [7:0]

Binary Operation (BCD_EN = 0) MON 01h 0Ch = The current month count.

7 6:0
IPGT

Reserved. 00h 7Fh: The number of octets of IPG.

EMAC PHY Read Status Data Registers Low and High Bytes EMAC_PRSD_L = 004Eh, EMAC_PRSD_H = 004Fh

7:0

EMAC_PRSD_x

0000h FFFFh: EMAC_PRSD_H = PRSD [15:8] EMAC_PRSD_L = PRSD [7:0]

Timer Reload Registers Low and High Byte TMR0_RR_L = 0063h, TMR1_RR_L= 0068h, TMR2_RR_L = 0072h, TMR3_RR_L = 0077h,TMR0_RR_H = 0064h, TMR1_RR_H= 0069h, TMR2_RR_H = 0073h, TMR3_RR_H = 0078h

7:0

Real-Time Clock Year Register RTC_YR = 00E6h Binary-Coded-Decimal Operation (BCD_EN = 1)

EMAC Non-Back-To-Back IPG Register Part 1 EMAC_IPGR1 = 002Eh

EMAC MII Status Register EMAC_MIISTAT = 0050h

7:0

TMR_RR_x

00h FFh: TMRx_RR_H = RELOAD [15:8] TMRx_RR_L = RELOAD [7:0]

7:4 3:0 7:0

7 6:0
IPGR1

Reserved. 00h 7Fh: The optional carrier sense window value.*

7 6 5 4:0

BUSY MIILF NVALID RDADR

1 = MII management operation in progress Busy.* 0 = Not busy. 1 = Local copy of PHY Link fail bit. 0 = PHY Link OK. 1 = MII Scan result is not valid Emac_PRSD is invalid. 0 = Emac_PRSD is valid. 00h 1Fh: Denotes PHY addressed in current scan cycle.

Flash Interrupt Control Register FLASH_IRQ = 00FBh

Timer Input Capture Control Register TMR1_CAP_CTL = 006Ah, TMR3_CAP_CTL= 007Bh

ZDI Bus Control Register ZDI_BUS_CTL = 17h*

TENS_YR YR

0 9 = The tens digit of the current year count. 0 9 = The ones digit of the current year count.

UART Line Status Registers UART0_LSR = 00C5h, UART1_LSR = 00D5h

7 6 5 4 3 2 1 0

DONE_IEN ERR_IEN DONE

0 = Flash Erase/Row Program Done Interrupt is disabled. 1 = Flash Erase/Row Program Done Interrupt is enabled. 0 = Error Condition Interrupt is disabled. 1 = Error Condition Interrupt is enabled. 0 = Erase/Row Program Done Flag is not set. 1 = Erase/Row Program Done Flag is set. Reserved.

7:4 3:2 1:0
CAP_EDGE_B

Reserved. 00 = Disable capture on ICB. 01 = Enable capture only on the falling edge of ICB. 10 = Enable capture only on the rising edge of ICB. 11 = Enable capture on both edges of ICB.

7 6 5:0

ZDI_BUSAK_EN ZDI_BUSAK

0 = Ignore external bus requests (BUSREQ).* 1 = Accept external bus requests (BUSREQ).* 0 = Deassert the bus acknowledge pin (BUSACK).* 1 = Assert the bus acknowledge pin (BUSACK).* Reserved.

Binary Operation (BCD_EN = 0) YR 00h 63h = The current year count.

EMAC Non-Back-To-Back IPG Register Part 2 EMAC_IPGR2 = 002Fh

7 6 5 4 3 2 1 0

ERR TEMT THRE BI FE PE OE DR

0 = Always 0 when operating with FIFO disabled.* 1 = Error detected in the FIFO.* 0 = THR/FIFO or SPI_TSR not empty, or transmitter not idle. 1 = Parity bit transmit and receive is enabled.* 0 = THR/FIFO is not empty. 1 = THR/FIFO is empty.* 0 = Receiver does not detect a BREAK condition.* 1 = Receiver detects a BREAK condition.* 0 = No framing error detected.* 1 = Framing error detected.* 0 = Received character does not contain a parity error.* 1 = Received character contains a parity error.* 0 = Received character does not contain an overrun error.* 1 = Overrun error is detected.* 0 = Reset to 0 when UARTx_RBR register is read.* 1 = Data ready.*

7 6:0
IPGR2

Reserved. 00h 7Fh: The non-back-to-back interpacket gap.

Real-Time Clock Century Register RTC_CEN = 00E7h Binary-Coded-Decimal Operation (BCD_EN = 1)

EMAC Receive Write Pointer Registers Low and High Bytes EMAC_RWP_L = 0051h, EMAC_RWP_H = 0052h

00 = Disable capture on ICA. 01 = Enable capture only on the falling edge of ICA. CAP_EDGE_A 10 = Enable capture only on the rising edge of ICA. 11 = Enable capture on both edges of ICA.

ZDI Instruction Store 4:0 Registers ZDI_IS4 = 21h, ZDI_IS3 = 22h, ZDI_IS2= 23h, ZDI_IS1= 24h, ZDI_IS0 = 25h*

7:0

EMAC_RWP_x

0000h 1FE0h: EMAC_RWP_H = RWP [15:8] EMAC_RWP_L = RWP [7:0]

WR_VIO RP_TMO PG_VIO MASS_VIO

0 = Write Violation Error Flag is not set. 1 = Write Violation Error Flag is set. 0 = Row Program Time-Out Error Flag is not set. 1 = Row Program Time-Out Error Flag is set. 0 = Page Erase Violation Error Flag is not set. 1 = Page Erase Violation Error Flag is set. 0 = Mass Erase Violation Error Flag is not set. 1 = Mass Erase Violation Error Flag is set.

7:4 3:0 7:0

TENS_CEN CEN

0 9 = The tens digit of the current century count. 0 9 = The ones digit of the current century count.

EMAC Maximum Frame Length Registers Low and High Bytes EMAC_MAXF_L = 0030h, EMAC_MAXF_H = 0031h

Timer Input Capture Value A Registers Low and High Bytes TMR1_CAPA_L = 006Bh, TMR3_CAPA_L = 007Ch, TMR1_CAPA_H = 006Ch, TMR3_CAPA_H = 007Dh

7:0

ZDI_IS4, ZDI_IS3, 00h FFh: ZDI_IS0 = INST [1st BYTE], ZDI_IS1 = INST [2nd BYTE], ZDI_IS2, ZDI_IS1, ZDI_IS2 = INST [3rd BYTE], ZDI_IS3 = INST [4th BYTE], or ZDI_IS0 ZDI_IS4 = INST [5th BYTE] *

EMAC Transmit Read Pointer Registers Low and High Bytes EMAC_TRP_L = 0053h, EMAC_TRP_H = 0054h

7:0

EMAC_MAXF_x

Binary Operation (BCD_EN = 0) CEN 00h 63h = The current century count.

0000h FFFFh: The Low/High byte of the 2-byte MAXF value {EMAC_MAXF_L [7:0] = MAXF [7:0], EMAC_MAXF_H [7:0] = MAXF [15:8]}

7:0

TMRx_CAPA_x

00h FFh: TMRx_CAPA_H = CAPTUREA [15:8] TMRX_CAPA_L = CAPTUREA [7:0]

ZDI Write Memory Register ZDI_WR_MEM = 30h*

7:0

EMAC_TRP_x

0000h 1FE0h: EMAC_TRP_H = TRP [15:8] EMAC_TRP_L = TRP [7:0]

EMAC Address Filter Register EMAC_AFR = 0032h

EMAC Receive Blocks Left Registers Low and High Bytes EMAC_BLKSLFT_L = 0055h, EMAC_BLKSLFT_H = 0056h

Flash Page Select Register FLASH_PAGE = 00FCh

Timer Input Capture Value B Registers Low and High Bytes TMR1_CAPB_L = 006Dh, TMR3_CAPB_L = 007Eh, TMR1_CAPB_H =006Eh, TMR3_CAPB_H = 007Fh

7:0

ZDI_WR_MEM

00h FFh: Byte written to ZDI_WR_MEM is also written to memory at address indicated by PC.

Real-Time Clock Alarm Seconds Register RTC_ASEC = 00E8h Binary-Coded-Decimal Operation (BCD_EN = 1)

7:4 3 2 1 0
PROM MC QMC BC

Reserved. 1 = Enable Promiscuous mode and disable station address filtering.* 0 = Disable Promiscuous mode. 1 = Accept any multicast message.* 0 = Do not accept multicast messages of any type. 1 = Accept only qualified multicast messages.* 0 = Do not accept qualified multicast messages. 1 = Accept broadcast messages.* 0 = Do not accept broadcast messages.

7:0

0000h FFFFh: EMAC_BLKSLFT_H = RBL [15:8] EMAC_BLKSLFT_x EMAC_BLKSLFT_L = RBL [7:0]

7 6:0

INFO_EN FLASH_PAGE

0 = Flash I/O access to main Flash memory. 1 = Flash I/O access to the information page.* 00h-7Fh: Page address of Flash memory to be used during the PAGE ERASE or I/O access of main Flash memory.*

7:0

TMRx_CAPB_x

00h FFh: TMRx_CAPB_H = CAPTUREB [15:8] TMRx_CAPB_L = CAPTUREB [7:0]

eZ80 Product ID Registers Low and High Bytes ZDI_ID_L = 00h, ZDI_ID_H = 01h

EMAC FIFO Data Register Low and High Bytes EMAC_FDATA_L = 0057h, EMAC_FDATA_H = 0058h

UART Modem Status Registers UART0_MSR = 00C6h, UART1_MSR = 00D6h

Timer Output Compare Control Register 1 TMR3_OC_CTL1 = 0080h

7:0

ZDI_ID_x

08h/00h: {ZDI_ID_H, ZDI_ID_L} = {00h, 08h} indicates the eZ80F91 product.*

7:4 3:0 7:0

ATEN_SEC ASEC

0 5 = The tens digit of the alarm seconds value. 0 9 = The ones digit of the alarm seconds value.

7:0

EMAC_FDATA_x

0000h 03FFh: EMAC_FDATA_H[1:0] = FD [9:8] EMAC_FDATA_L = FD [7:0]

7 6 5 4 3 2 1 0

DCD RI DSR CTS DDCD TERI DDSR DCTS

0 1: Data Carrier Detect.* 0 1: Ring Indicator.* 0 1: Data Set Ready.* 0 1: Clear To Send.* 0 1: Delta status change of Data Carrier Detect.* 0 1: Trailing Edge change on Ring Indicator.* 0 1: Delta status change of Data Set Ready.* 0 1: Delta status change of Clear To Send.*

Flash Row Select Register FLASH_ROW = 00FDh

7:6
Reserved.

Unused. OCx_INIT X[3:0] MAST_MODE OC_EN 0 = OC pin cleared when initialized. 1 = OC pin set when initialized. 0 = OC pins are independent. 1 = OC pins all mimic OC0. 0 = OUTPUT COMPARE mode is disabled. 1 = OUTPUT COMPARE mode is enabled.

eZ80 Product ID Revision Register ZDI_ID_REV = 02*

7:3 2:0
FLASH_ROW

5:2 1 0

7:0

ZDI_ID_REV

00h FFh: Identifies the current revision of the eZ80F91 product.

Binary Operation (BCD_EN = 0) ASEC 00h 3Bh = The alarm seconds value.

EMAC FIFO Flags Register EMAC_FFLAGS = 0059h

0h 7h: Row address of Flash memory to be used during an I/O access of Flash memory.*

Real-Time Clock Alarm Minutes Register RTC_AMIN = 00E9h Binary-Coded-Decimal Operation (BCD_EN = 1)

EMAC Hash Table Registers EMAC_HTBL_0 = 0033h, EMAC_HTBL_1 = 0034h, EMAC_HTBL_2 = 0035h, EMAC_HTBL_3 = 0036h, EMAC_HTBL_4 = 0037h, EMAC_HTBL_5 = 0038h, EMAC_HTBL_6 = 0039h, EMAC_HTBL_7 = 003Ah

7 6 5 4 3 2 1 0

TFF

1 = Transmit FIFO full. 0 = Transmit FIFO not full. Reserved.

ZDI Status Register ZDI_STAT = 03h*

Flash Column Select Register FLASH_COL = 00FEh

7 6 5 4 3 2 1:0

ZDI_ACTIVE

0 = CPU is not functioning in ZDI mode. 1 = CPU is currently functioning in ZDI mode. Reserved.

TFAE TFE RFF RFAF RFAE RFE

7:4 3:0 7:0

ATEN_MIN AMIN

0 5 = The tens digit of the alarm minutes value. 0 9 = The ones digit of the alarm minutes value.

7:0

EMAC_HTBL_x

00h FFh: 64 bit hash table = {EMAC_HTBL_7, EMAC_HTBL_6, EMAC_HTBL_5, EMAC_HTBL_4, EMAC_HTBL_3, EMAC_HTBL_2, EMAC_HTBL_1, EMAC_HTBL_0}*

1 = Transmit FIFO almost empty. 0 = Transmit FIFO not almost empty. 1 = Transmit FIFO empty. 0 = Transmit FIFO not empty. 1 = Receive FIFO full. 0 = Receive FIFO not full. 1 = Receive FIFO almost full. 0 = Receive FIFO not almost full. 1 = Receive FIFO almost empty. 0 = Receive FIFO not almost empty. 1 = Receive FIFO empty. 0 = Receive FIFO not empty.

7:0

FLASH_COL

00h FFh: Column address of Flash memory to be used during an I/O access of Flash memory.

Timer Output Compare Control Register 2 TMR3_OC_CTL2 = 0081h

Flash Program Control Register FLASH_PGCTL = 00FFh

7:0

OCx_MODE X[3:0]

7:3 2 1 0
ROW_PGM PG_ERASE MASS_ERASE

Reserved. 0 = Row Program Disable or Row Program completed. 1 = Row Program Enable.* 0 = Page Erase Disable.* 1 = Page Erase Enable.* 0 = Mass Erase Disable.* 1 = Mass Erase Enable.*

00 = Initialize OC pin to value specified in TMR3_OC_CTL1.* 01 = OC pin is cleared upon timer compare. 10 = OC pin is set upon timer compare. 11 = OC pin toggles upon timer compare.

HALT_SLP ADL MADL IEF1 RESERVED

0 = CPU is not currently in HALT or SLEEP mode. 1 = CPU is currently in HALT or SLEEP mode. 0 = CPU is operating in Z80 MEMORY mode.* 1 = CPU is operating in ADL MEMORY mode.* 0 = CPU s Mixed-Memory mode (MADL) bit is reset to 0. 1 = CPU s Mixed-Memory mode (MADL) bit is set to 1. 0 = CPU s Interrupt Enable Flag 1 is reset to 0.* 1 = CPU s Interrupt Enable Flag 1 is set to 1.* Reserved.

Binary Operation (BCD_EN = 0) AMIN 00h 3Bh = The alarm minutes value.

EMAC MII Management Register EMAC_MIIMGT = 003Bh

UART Scratch Pad Registers UART0_SPR = 00C7h, UART1_SPR = 00D7h

7 6 5 4 3 2:0

LCTLD RSTAT SCINC SCAN SPRE

1 = Rising edge causes the CTLD control data to be transmitted. * 0 = No operation. 1 = Rising edge causes status to be read from external PHY.* 0 = No operation. 1 = Scan PHY address increments upon SCAN cycle.* 0 = Normal operation. 1 = Perform continuous Read cycles via MII management.* 0 = Normal operation. 1 = Suppress MDO preamble. 0 = Normal preamble. 000 001 010 011 MDC = SCLK 4 MDC = SCLK 4 MDC = SCLK 6 MDC = SCLK 8 100 MDC = SCLK 10 101 MDC = SCLK 14 110 MDC = SCLK 20 111 MDC = SCLK 28

Real-Time Clock Alarm Hours Register RTC_AHRS = 00EAh Binary-Coded-Decimal Operation (BCD_EN = 1)

7:0

SPR

00h FFh: UART scratch pad register is available for use as a general-purpose Read/Write register. In multi-drop 9 bit mode, this register is used to store the address value.

Timer Output Compare Value Registers Low and High Bytes TMR3_OC0_L = 0082h, TMR3_OC1_L = 0084h,TMR3_OC2_L = 0086h, TMR_OC3_L = 0088h,TMR3_OC0_H = 0082h, TMR3_OC1_H = 0084h, TMR3_OC2_H = 0086h, TMR_OC3_H = 0088h

7:0

TMR3_OCx_x

00h FFh: TMR3_OCx_H = COMPARE [15:8] TMR3_OCx_L = COMPARE [7:0]

ZDI Read Registers Low, High and Upper ZDI_RD_L = 10h, ZDI_RD_H = 11h, ZDI_RD_U= 12h*

7:4 3:0 7:0

ATEN_HRS AHRS

0 2 = The tens digit of the alarm hours value. 0 9 = The ones digit of the alarm hours value.

7:0

Binary Operation (BCD_EN = 0) AHRS 00h 17h = The alarm hours value.

SPI Registers
JP1 Peripheral Bus External Connector JP2 I/O External Connector J3 GPRS Modem Connectors
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17

ZDI_RD_L, ZDI_RD_H, or ZDI_RD_U

000000h FFFFFFh: Read Control register during a ZDI Read operation. {ZDI_RD_U = RDATA [23:16], ZDI_RD_H = RDATA [15:8], ZDI_RD_L = RDATA [7:0]}

CLKS

SPI Baud Rate Generator Register Low Byte SPI_BRG_L = 00B8h

ZDI Read Memory Register ZDI_RD_MEM = 20h*

eZ80F91 Modular Adapter Board with Mini Enet Module
JP1 JP2 JP12

Real-Time Clock Alarm Day-of-the-Week Register RTC_ADOW = 00EBh Binary-Coded-Decimal Operation (BCD_EN = 1)

EMAC PHY Configuration Data Register Low and High Bytes EMAC_CTLD_L = 003Ch, EMAC_CTLD_H = 003Dh

7:0

SPI_BRG_L

00h FFh: These bits represent the Low byte of the 16-bit Baud Rate Generator divider value.*

7:0

ZDI_RD_MEM

00h FFh: 8-bit data Read from the memory address indicated by the CPU s Program Counter.*

7:4 3:0 7:4 3:0
ADOW ADOW

7:0

EMAC_CTLD_x

00h FFh: Low/High byte of the 2-byte PHY configuration data value {EMAC_CTLD_H, EMAC_CTLD_L}.*
1 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60

SPI Baud Rate Generator Register High Byte SPI_BRG_H = 00B9h
GND VCC_5V

Reserved. 1 7 = The alarm day-of-the-week value. EMAC PHY Address Register EMAC_RGAD= 003Eh
TRSTN F91_WE GND A6 A10 GND A8 A13 A15 A18 A19 A2 A11 A4 A5 A21 A22 CSO CS2 D1 D3 D5 D7 MREQ GND WR BUSACK

3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59

Binary Operation (BCD_EN = 0) Reserved. 01h 07h = The alarm day-of-the-week value.

7:5 4:0
RGAD

Reserved. 00h 1Fh: 5-bit address of external PHY unit registers.

Real-Time Clock Alarm Control Register RTC_ACTRL = 00ECh

7:4 3 2 1 0
ADOW_EN AHRS_EN AMIN_EN ASEC_EN

Reserved. 0 = The day-of-the-week alarm is disabled. 1 = The day-of-the-week alarm is enabled. 0 = The hours alarm is disabled. 1 = The hours alarm is enabled. 0 = The minutes alarm is disabled. 1 = The minutes alarm is enabled. 0 = The seconds alarm is disabled. 1 = The seconds alarm is enabled.

RAM Control Registers
RAM Control Register RAM_CTL = 00B4h

7 6 5:0

GPRAM_EN ERAM_EN

0 = On-chip general-purpose RAM is disabled. 1 = On-chip general-purpose RAM is enabled. 0 = On-chip EMAC RAM is disabled. 1 = On-chip EMAC RAM is enabled. Reserved.

VCC_33V A0 A3 VCC_33V A7 A9 A14 A16 GND A1 A12 A20 A17 DIS_FLASH VCC_33V A23 CS1 D0 D2 D4 GND D6 IOREQ RD INSTRD BUSREQ

PA7 PA5 PA3 PA1 VCC_33V PB7 PB5 PB3 PB1 GND PC6 PC4 PC2 PC0 PD6 PD5 PD3 P03 PD1 P01 TDO GND TCK RTC_VDD IICSCL IICSDA FLASHWE CS3 RST VCC_33V HALT_SLP VCC_33V

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60

PA6 PA4 PA2 PA0 GND PB6 PB6 PB4 PB2 PB0 PC7 PC5 PC3 PC1 PD7 GND PD4 PD2 PD2 PD0 PD0 TDI TRIGOUT TMS EZ80CLK GND DIS_IRDA WAIT GND NMI

GND

7:0

SPI_BRG_H

00h FFh: These bits represent the High byte of the 16-bit Baud Rate Generator divider value.*

J12
1 2

SPI Control Register SPI_CTL = 00BAh

Interrupt Controller
Priority Priority Control Bit Vector Source

HEADER 2

7 6 5 4 3
GND PC4_DTR1 PC6_DCD1 PC3_CTS1 PC5_DSR1 PC7_RI1 PC0_TXD1 PC1_RXD1 PC2_RTS1 PC4 PC6 PC3 PC5 PC7 PC0 PC1 PC2

IRQ_EN

0 = SPI system interrupt is disabled. 1 = SPI system interrupt is enabled. Reserved.

Interrupt Vector Sources by Priority INT_P0 = 0010h, INT_P1 = 0011h, INT_P2 = 0012h INT_P3 = 0013h, INT_P4 = 0014h, INT_P5 = 0015h Priority Priority Control Bit Vector Source

SPI_EN MASTER_EN CPOL CPHA

0 = SPI is disabled. 1 = SPI is enabled. 0 = When enabled, the SPI operates as a slave. 1 = When enabled, the SPI operates as a master. 0 = Master SCK pin idles in a Low (0) state. 1 = Master SCK pin idles in a High (1) state. 0 = SS must go High after every data byte transfer. 1 = SS can remain Low to transfer any number of data bytes. Reserved.

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23

INT_P0[0] INT_P0[1] INT_P0[2] INT_P0[3] INT_P0[4] INT_P0[5] INT_P0[6] INT_P0[7] INT_P1[0] INT_P1[1] INT_P1[2] INT_P1[3] INT_P1[4] INT_P1[5] INT_P1[6] INT_P1[7] INT_P2[0] INT_P2[1] INT_P2[2] INT_P2[3] INT_P2[4] INT_P2[5] INT_P2[6] INT_P2[7]

040h 044h 048h 04Ch 050h 054h 058h 05Ch 060h 064h 068h 06Ch 070h 074h 078h 07Ch 080h 084h 088h 08Ch 090h 094h 098h 09Ch

EMAC Rx EMAC Tx EMAC SYS PLL Flash Timer 0 Timer 1 Timer 2 Timer 3 unused* unused* RTC UART 0 UART 1 I2C SPI Port A 0 Port A 1 Port A 2 Port A 3 Port A 4 Port A 5 Port A 6 Port A 7

24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47

INT_P3[0] INT_P31] INT_P3[2] INT_P3[3] INT_P3[4] INT_P3[5] INT_P3[6] INT_P3[7] INT_P4[0] INT_P4[1] INT_P4[2] INT_P4[3] INT_P4[4] INT_P4[5] INT_P4[6] INT_P4[7] INT_P5[0] INT_P5[1] INT_P5[2] INT_P5[3] INT_P5[4] INT_P5[5] INT_P5[6] INT_P5[7]

0A0h 0A4h 0A8h 0ACh 0B0h 0B4h 0B8h 0BCh 0C0h 0C4h 0C8h 0CCh 0D0h 0D4h 0D8h 0DCh 0E0h 0E4h 0E8h 0ECh 0F0h 0F4h 0F8h 0FCh

Port B 0 Port B 1 Port B2 Port B3 Port B4 Port B5 Port B6 Port B7 Port C0 Port C1 Port C2 Port C3 Port C4 Port C5 Port C6 Port C7 Port D0 Port D1 Port D2 Port D3 Port D4 Port D5 Port D6 Port D7

J11
RST GND
1 2 3 4 5 6 7 8 9

19 20 21 22 23 24 25 26 27 28

2 1:0

29 30 31 32

HEADER 9

SPI Status Register SPI_SR = 00BBh

Real-Time Clock Control Register RTC_CTRL = 00EDh

7 6 5 4 3 2 1 0

ALARM INT_EN BCD_EN CLK_SEL FREQ_SEL DAY_SAV SLP_WAKE RTC_UNLOCK

0 = Alarm interrupt is inactive. 1 = Alarm interrupt is active. 0 = Interrupt on alarm condition is disabled. 1 = Interrupt on alarm condition is enabled. 0 = RTC count and alarm value registers are binary. 1 = RTC count and alarm value registers are binary-coded decimal. 0 = RTC clock source is crystal oscillator output.* 1 = RTC clock source is power-line frequency input.* 0 = Power-line frequency is 60 Hz. 1 = Power-line frequency is 50 Hz. 0 = Daylight Savings Time not selected. 1 = Daylight Savings Time selected. 0 = RTC does not generate a sleep-mode recovery reset. 1 = RTC Alarm generates a sleep-mode recovery reset. 0 = RTC count registers are locked to prevent write access.* 1 = RTC count registers are unlocked to allow write access.*

RAM Address Upper Byte Register RAM_ADDR_U = 00B5h

7:0

RAM_ADDR_U

00h FFh: This byte define the upper byte of the RAM address.*

CAUTION: The following signals are not connected and are unavailable on the associated pins: Pin 36, DIS_Flash Pin 42, CS1 Pin 53, MREQ Pin 54, IOREQ Pin 58, INSTRD Pin 59, BUSACK Pin 60, BUSREQ

CAUTION: The signal on Pin 49, FlashWE, is not connected and is unavailableon the associated pin.

HEADER 32

JP11

7 6 5 4 3:0

SPIF WCOL

0 = SPI data transfer is not finished. 1 = SPI data transfer is finished.* 0 = An SPI write collision is not detected. 1 = An SPI write collision is detected.* Reserved.

eZ80F91 Modular Adapter Board Interfaces

MODF

0 = A mode fault (multimaster conflict) is not detected. 1 = A mode fault (multimaster conflict) is detected.* Reserved.

MBIST Control Register MBIST_GPR = 00B6h, MBIST_EMR = 00B7h

7 6 5 4:0

MBIST_ON MBIST_DONE MBIST_PASS

0 = MBIST Testing of the RAM is disabled. 1 = MBIST Testing of the RAM is enabled. 0 = MBIST Testing has not completed. 1 = MBIST Testing has completed. 0 = MBIST Testing has failed. 1 = MBIST Testing has passed. Reserved.

SPI Transmit Shift Register SPI_TSR = 00BCh

L
Read/Write Read Only

E
Write Only

D
Reserved

7:0

TX_DATA

00h FFh: SPI transmit data.

Unique parameter-dependent Read/Write behavior

SPI Receive Buffer Register SPI_RBR = 00BCh

7:0

RX_DATA

00h FFh: SPI received data.

Note: Each bit sets the Internet Priority Level for the given device. 0 = Default Level 0, 1 = Higher Level 1

*Zilog has exercised all efforts to ensure accuracy. Should you find discrepancies, please consult the eZ80F91 Product Specification (PS0192).
FL006903-0208

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